{"title":"Beyond Classical Transport: NEGF-Based Unveiling of Ferroelectric Charge-Plasma Vertical Nanowire Dynamics","authors":"Preeti Singh;Maneesha Gupta;Prabhat Singh;Prateek Kumar;Naveen Kumar","doi":"10.1109/TDEI.2026.3701368","DOIUrl":null,"url":null,"abstract":"The theoretical 60 mV/dec subthreshold swing limit of conventional MOSFETs has motivated the exploration of alternative device architectures and materials. This work investigates the effect of embedding a ferroelectric (FE) layer in an ultrascaled vertical charge-plasma nanowire FET (VNW-FET). Unlike most previously reported FE–nanowire devices that employ channel lengths <inline-formula> <tex-math>$\\ge 30$ </tex-math></inline-formula>–100 nm, thicker FE layers, and are mainly targeted for memory applications, this study analyzes a 15 nm vertical nanowire with a 1.5 nm FE layer in a dopingless charge-plasma configuration. Quantum transport is modeled using mode-space nonequilibrium green’s function (NEGF) coupled with Schrödinger–Poisson equations, enabling energy-resolved analysis of transmission probability and density of states (DOSs). The influence of temperature, FE length, and FE thickness on C–V<sub>GS</sub> and I<sub>DS</sub>–V<sub>GS</sub> characteristics is examined. Results show that FE integration predominantly affects the <inline-formula> <tex-math>${\\mathrm {I}}_{\\textit {ON}}$ </tex-math></inline-formula>, where shifts in transmission threshold and DOS redistribution enhance I<sub>ON</sub>. Increasing FE length further improves I<sub>ON</sub>, and the FE/SiO<sub>2</sub> stack enhances the I<sub>ON</sub>/I<sub>OFF</sub> ratio by more than an order of magnitude. The device is also evaluated for NH<sub>3</sub> and H<sub>2</sub> sensing using the Gouy–Chapman–Stern framework.","PeriodicalId":13247,"journal":{"name":"IEEE Transactions on Dielectrics and Electrical Insulation","volume":"33 5","pages":"3510-3516"},"PeriodicalIF":3.3000,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Dielectrics and Electrical Insulation","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11556326/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"2026/6/9 0:00:00","PubModel":"Epub","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
The theoretical 60 mV/dec subthreshold swing limit of conventional MOSFETs has motivated the exploration of alternative device architectures and materials. This work investigates the effect of embedding a ferroelectric (FE) layer in an ultrascaled vertical charge-plasma nanowire FET (VNW-FET). Unlike most previously reported FE–nanowire devices that employ channel lengths $\ge 30$ –100 nm, thicker FE layers, and are mainly targeted for memory applications, this study analyzes a 15 nm vertical nanowire with a 1.5 nm FE layer in a dopingless charge-plasma configuration. Quantum transport is modeled using mode-space nonequilibrium green’s function (NEGF) coupled with Schrödinger–Poisson equations, enabling energy-resolved analysis of transmission probability and density of states (DOSs). The influence of temperature, FE length, and FE thickness on C–VGS and IDS–VGS characteristics is examined. Results show that FE integration predominantly affects the ${\mathrm {I}}_{\textit {ON}}$ , where shifts in transmission threshold and DOS redistribution enhance ION. Increasing FE length further improves ION, and the FE/SiO2 stack enhances the ION/IOFF ratio by more than an order of magnitude. The device is also evaluated for NH3 and H2 sensing using the Gouy–Chapman–Stern framework.
期刊介绍:
Topics that are concerned with dielectric phenomena and measurements, with development and characterization of gaseous, vacuum, liquid and solid electrical insulating materials and systems; and with utilization of these materials in circuits and systems under condition of use.