Symmetric Fractional-Order LADRC-PLL With Impedance Reshaping for Grid-Connected Inverter in Weak Grid

Abstract

In weak grid conditions, the interaction between the phase-locked loop (PLL) and the grid impedance can introduce negative damping, potentially exciting low-frequency oscillations that impair the stability of a grid-connected inverter (GCI). Although the linear active disturbance rejection control (LADRC) approach can strengthen PLL robustness, it still exhibits limitations in suppressing the frequency coupling effect (FCE) and in improving dynamic response. To overcome these issues, a symmetric fractional-order LADRC-PLL is proposed, which incorporates an impedance reshaping strategy to further improve the stability of the GCI. First, the influence of the fractional-order operators on the dynamic characteristics of the PLL and the output impedance of the GCI is analyzed through frequency-domain modeling, revealing the intrinsic mechanism responsible for the introduction of negative damping. Then, a composite phase compensation filter is designed to enhance the phase margin of the output impedance, whereas a real-time frequency estimation–based phase angle correction method is employed to mitigate voltage–current phase errors caused by frequency deviations. The effectiveness of the proposed approach in mitigating FCE, enhancing dynamic performance of the PLL, and reinforcing stability under weak grid conditions is confirmed through simulation and hardware-in-the-loop (HIL) experiments.