An Ultra-Low-Power Biopotential Acquisition Analog Front-End Chip for Wearable Devices

IF 1.4 3区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
Zhang Xin, Yang Tianqi, Xu Wei, Wang Shun, Xiaoxi Ma
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引用次数: 0

Abstract

A 0.8-V, 1.2-μW biopotential analog front-end (AFE) IC is presented for wearable sensing. The front end combines a dynamically biased, chopper-stabilized capacitively coupled instrumentation amplifier (CCIA) with a dual-time-scale electrode dc-offset (EDO) management path. In steady state, a low-leakage DC servo loop (DSL) preserves sub-Hz baseline restoration and > 1 GΩ input impedance at 10 Hz; after an abrupt EDO disturbance, an event-triggered fast-recovery path temporarily increases the low-frequency discharge conductance and then returns to the low-leakage state. The 0.18-μm CMOS core occupies 0.35 mm2, provides 60- to 100-dB programmable gain, and consumes 1.2 μW from 0.8 V. Without trimming, calibration codes, or postmeasurement mismatch compensation, the measured input-referred integrated noise is 0.98 μVrms over 0.5–100 Hz, with CMRR > 125 dB, PSRR > 98 dB at 10 Hz, and > 1 GΩ input impedance at 10 Hz under the calibrated balanced bench fixture. New quantitative robustness validation shows postlayout PVT ranges of 121.8–127.9 dB for CMRR, 94.6–101.0 dB for PSRR, 0.93–1.07 μVrms for input-referred noise, and 53–82 ms for fast-recovery time; 200-run mismatch Monte Carlo analysis gives CMRR = 126.4 ± 2.7 dB, PSRR = 99.1 ± 2.1 dB, and input-referred offset = 0.08 ± 0.34 mV. For the representative EDO-step emulation, the fast-recovery mode returns to the sustained linear region in approximately 60–70 ms, whereas the DSL-only response remains unsettled at the 300-ms observation limit.

用于可穿戴设备的超低功耗生物电位采集模拟前端芯片
提出了一种用于可穿戴传感的0.8 v、1.2 μ w生物电位模拟前端(AFE) IC。前端结合了动态偏置、斩波稳定电容耦合仪表放大器(CCIA)和双时间尺度电极直流偏置(EDO)管理路径。在稳定状态下,低漏直流伺服环路(DSL)保持亚Hz基线恢复和10hz输入阻抗>; 1 GΩ;事件触发的快速恢复路径在受到突发性EDO干扰后,会暂时增加低频放电电导,然后恢复到低漏状态。0.18 μm CMOS核心占地0.35 mm2,提供60至100db的可编程增益,功耗为1.2 μW,电压为0.8 V。在校准的平衡台式夹具下,在不进行微调、校准码或测量后失配补偿的情况下,测量到的输入参考集成噪声在0.5 ~ 100 Hz范围内为0.98 μVrms, CMRR > 125 dB, PSRR > 98 dB, 10hz输入阻抗>; 1 GΩ。新的定量鲁棒性验证表明,布局后的PVT范围为CMRR 121.8 ~ 127.9 dB, PSRR 94.6 ~ 101.0 dB,输入参考噪声0.93 ~ 1.07 μVrms,快速恢复时间53 ~ 82 ms;200跑失配蒙特卡罗分析得到CMRR = 126.4±2.7 dB, PSRR = 99.1±2.1 dB,输入参考偏置= 0.08±0.34 mV。对于代表性的edo阶跃仿真,快速恢复模式在大约60-70 ms内返回到持续线性区域,而仅dsl响应在300 ms的观测极限下仍然不稳定。
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来源期刊
International Journal of Circuit Theory and Applications
International Journal of Circuit Theory and Applications 工程技术-工程:电子与电气
CiteScore
3.60
自引率
34.80%
发文量
277
审稿时长
4.5 months
期刊介绍: The scope of the Journal comprises all aspects of the theory and design of analog and digital circuits together with the application of the ideas and techniques of circuit theory in other fields of science and engineering. Examples of the areas covered include: Fundamental Circuit Theory together with its mathematical and computational aspects; Circuit modeling of devices; Synthesis and design of filters and active circuits; Neural networks; Nonlinear and chaotic circuits; Signal processing and VLSI; Distributed, switched and digital circuits; Power electronics; Solid state devices. Contributions to CAD and simulation are welcome.
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