CT-LNN: FPGA-Based Accelerator for Continuous-Time Liquid Neural Networks

Abstract

Human Activity Recognition (HAR) based on multivariate time-series data is a representative edge intelligence workload. However, conventional deep neural networks, such as Convolutional Neural Networks (CNNs) and Recurrent Neural Networks (RNNs), suffer from limited FPGA efficiency due to sequential dependencies, irregular memory access patterns, and large model sizes. This paper presents an end-to-end FPGA acceleration framework for Liquid Neural Network (LNN)-based real-time HAR. By exploiting closed-form continuous-time dynamics, the proposed approach enables parallel computation while preserving temporal modeling capability. Several algorithm–hardware co-design techniques are introduced to improve efficiency. An accuracy-aware power-of-two quantization scheme reduces bit width with a small accuracy loss, and a hardware-efficient activation approximation based on combinational logic eliminates transcendental operations. In addition, a contention-aware dataflow architecture with optimized multi-channel communication and hierarchical memory organization is developed. An optimized matrix–vector multiplication engine with 8-way cyclic banking is further implemented to enable conflict-free parallel access. The design is implemented on an Artix-7 FPGA and evaluated on the UCI ConfLongDemo_JSI dataset, achieving 94.34% accuracy with $688~\mu $ s latency and 15.12 GOPS throughput. The complete Zynq-7020 system consumes 1.81 W, including both the ARM Cortex-A9 processing system and the programmable logic, while the CT-LNN module on the PL side consumes 264 mW. Based on the total system power, the accelerator achieves 8.35 GOPS/W energy efficiency, demonstrating an efficient and scalable solution for edge deployment.