Address Matters: Modeling Boundaries of Bandwidth–Latency Memory Simulation

Abstract

Analytical memory simulators that assign latency from bandwidth–latency curves profiled on real hardware promise real-system fidelity without microarchitectural detail. We measure where this abstraction breaks, taking the Mess simulator as an exemplar. Its runtime state—aggregate bandwidth and read/write ratio—conceals the access-pattern effects that govern real memory behavior. Controlled real-system measurements show that channel skewness causes up to 4.7 × latency variation at equal aggregate bandwidth and a 4.2 × saturation-bandwidth gap, while row-buffer locality and read/write ordering induce 36.4% and 21.3% latency variation. Its fixed window size and convergence factor further produce up to 194.5% parameter sensitivity across SPEC CPU workloads with different memory intensities. Reducing these discrepancies requires address- and phase-aware runtime signals. Our proof-of-concept ($\text{Mess}^+$) tracks per-channel traffic using physical addresses, reducing the IPC divergence with Ramulator2 by 49.1% under channel-skewed traffic. The open challenge is incorporating additional signals without collapsing the lightweight abstraction into detailed timing simulation.