An Ising machine for combinatorial optimization based on sub-nanosecond CMOS-integrated magnetoresistive random-access memory

Abstract

Physics-inspired Ising machines are a hardware alternative to traditional von Neumann architectures for solving computationally intensive combinatorial optimization problems. They can be implemented using quantum, optical and electronic platforms, but speed and scalability are fundamentally limited by the physical mechanisms governing their spin dynamics. Here we report a complementary-metal–oxide–semiconductor-integrated spintronic Ising machine with sub-nanosecond probabilistic spin updates. We use the voltage-controlled magnetic anisotropy effect in a magnetoresistive random-access memory with 96,000 spins to achieve low write currents and tunable (from 0% to 100%) single-pulse switching probability via pulse-width control. The approach offers a spin update speed of 0.3 to 1 ns and an energy efficiency of less than 40 fJ per spin. We illustrate the generality of this on-chip all-to-all Ising machine by solving industry-relevant combinatorial optimization problems in electronic design automation: global routing and layer assignment. Tested with Max-cut benchmark problems, our Ising machine can provide high-quality solutions with a system energy efficiency of 1.92 × 105 solutions per second per watt. A complementary-metal–oxide–semiconductor-integrated spintronic Ising machine has a spin update speed of 0.3 to 1 ns and an energy efficiency of less than 40 fJ per spin, and can solve Max-cut problems with a system energy efficiency of 1.92 × 105 solutions per second per watt.