An Autonomous Hazard-Resolving MAC Unit With Conditional Reduction for DRAM-PIM

Abstract

Processing-in-Memory (PIM) is a pivotal solution for accelerating memory-intensive AI workloads like General Matrix-Vector Multiplication (GEMV). However, the inherent speed limitations of DRAM process technology necessitate multi-cycle pipelined MAC units, which introduce critical accumulation hazards. Current industry solutions resolve these hazards by either sacrificing computational precision, compromising memory layout flexibility, or requiring invasive modifications to the host-side memory controller. This paper proposes Conditional Reduction, an autonomous hardware-based scheme that resolves accumulation hazards entirely within the PIM unit without host or controller intervention. By bridging the information asymmetry between the memory controller and internal DRAM pipeline states, our scheme triggers reduction only when data dependencies are detected. Utilizing a register-renaming mechanism with only five additional entries, the proposed architecture minimizes silicon overhead while maintaining strict JEDEC-standard compatibility. Experimental evaluations on LPDDR5X-9600 demonstrate that Conditional Reduction achieves up to a 1.504× speedup over conventional double-register approaches by eliminating explicit software fences and redundant reduction phases. Furthermore, it reduces the area overhead by 6.94% for a 2 kb output register configuration, offering a scalable and future-proof solution for high-performance DRAM-PIM architectures.