{"title":"LLM KV Cache Storage Using CXL Memory","authors":"Kwan Huen;Gongjin Sun;Mehdi Nik;Caroline Kahn;Elham Movahedian;Senthil Murugesapandian;Michael Wasef;Shuyu Lyu;Dongyang Li;Edmund Au;Brian Luu;Jason Scott;Ranjitha Gopalakrishna;Namita Kumar;Amir Beygi;Vitorio Cargnini;Ramdas Kachare","doi":"10.1109/LCA.2026.3720952","DOIUrl":null,"url":null,"abstract":"As the memory need for KV cache grows rapidly with the advent of multi-turn inferences and extremely long context requirements, limited GPU memory has become a critical bottleneck. While offloading the KV cache to CPU DRAM or SSDs has been explored, these solutions face limitations in capacity, latency, and scalability. Compute Express Link (CXL) memory offers a promising alternative that provides low-latency, disaggregation, and scalability benefits. In this paper, we evaluate KV cache offloading using various novel CXL memory architectures to compare with existing solutions. We tested memory expanders, CMM-D and CMM-H, and memory pooling solutions, including CMM-B and CMM-MP. For performance evaluation, vLLM, coupled with the LMCache framework, is employed to characterize five offloading targets. This comprehensive study provides insights into KV cache offloading tiers that can be used by end users to optimize their AI data center system architectures. CXL memory devices show significant performance benefits for KV cache offloading, with CMM-MP’s novel memory pooling architecture offering a particularly scalable and cost-efficient solution.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 2","pages":"319-322"},"PeriodicalIF":2.0000,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11642129","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Computer Architecture Letters","FirstCategoryId":"94","ListUrlMain":"https://ieeexplore.ieee.org/document/11642129/","RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"2026/8/6 0:00:00","PubModel":"Epub","JCR":"Q4","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
As the memory need for KV cache grows rapidly with the advent of multi-turn inferences and extremely long context requirements, limited GPU memory has become a critical bottleneck. While offloading the KV cache to CPU DRAM or SSDs has been explored, these solutions face limitations in capacity, latency, and scalability. Compute Express Link (CXL) memory offers a promising alternative that provides low-latency, disaggregation, and scalability benefits. In this paper, we evaluate KV cache offloading using various novel CXL memory architectures to compare with existing solutions. We tested memory expanders, CMM-D and CMM-H, and memory pooling solutions, including CMM-B and CMM-MP. For performance evaluation, vLLM, coupled with the LMCache framework, is employed to characterize five offloading targets. This comprehensive study provides insights into KV cache offloading tiers that can be used by end users to optimize their AI data center system architectures. CXL memory devices show significant performance benefits for KV cache offloading, with CMM-MP’s novel memory pooling architecture offering a particularly scalable and cost-efficient solution.
随着多回合推理和超长上下文需求的出现,千伏缓存的内存需求迅速增长,有限的GPU内存已成为关键瓶颈。虽然已经探索了将KV缓存卸载到CPU DRAM或ssd上,但这些解决方案在容量、延迟和可扩展性方面存在限制。Compute Express Link (CXL)内存提供了一种很有前途的替代方案,它提供了低延迟、分解和可伸缩性优势。在本文中,我们评估了使用各种新型CXL内存架构的KV缓存卸载,并与现有解决方案进行了比较。我们测试了内存扩展器、CMM-D和CMM-H,以及内存池解决方案,包括CMM-B和CMM-MP。为了进行性能评估,使用vLLM和LMCache框架对5个卸载目标进行表征。这项全面的研究提供了千伏缓存卸载层的见解,最终用户可以使用它来优化他们的人工智能数据中心系统架构。CXL存储设备在KV缓存卸载方面表现出显著的性能优势,CMM-MP新颖的内存池架构提供了一种特别可扩展且经济高效的解决方案。
期刊介绍:
IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.