Zhao Zhang;Pengrong Lin;Zixiong Song;Tiening Wang;Ruohan Zhang;Peng Gao;Yimao Cai;Yong Wang
{"title":"An Overview of Chiplet and Integrated Chip Testing Technologies","authors":"Zhao Zhang;Pengrong Lin;Zixiong Song;Tiening Wang;Ruohan Zhang;Peng Gao;Yimao Cai;Yong Wang","doi":"10.23919/cje.2025.00.160","DOIUrl":null,"url":null,"abstract":"Chiplet and integrated chip technologies, one of the mainstream methods to enhance chip performance in the post-Moore era, have garnered significant attention from academia and industry. Testing technology plays a crucial role in ensuring the reliability and functionality of the product, and is a key area that requires breakthroughs in the development of chiplets and integrated chips. This paper offers a comprehensive overview of chiplet and integrated chip testing technologies, analyzing the current research status and challenges encountered in this critical field. In this paper, we first explore the testing process of integrated chips, including design for test (DfT), Known Good Die testing, integrated module testing, final testing, and system-level testing. The current research trends in integrated chip testing are reviewed, focusing on system-level DfT techniques and inter-chiplet interconnection testing methods. This article also introduces the testing equipment and fixtures required for integrated chip testing, as well as electronic design automation tools. Finally, the challenges and future directions faced by integrated chip testing technology are explored.","PeriodicalId":50701,"journal":{"name":"Chinese Journal of Electronics","volume":"35 4","pages":"1607-1630"},"PeriodicalIF":4.5000,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11685238","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Chinese Journal of Electronics","FirstCategoryId":"94","ListUrlMain":"https://ieeexplore.ieee.org/document/11685238/","RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"2026/9/9 0:00:00","PubModel":"Epub","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
Chiplet and integrated chip technologies, one of the mainstream methods to enhance chip performance in the post-Moore era, have garnered significant attention from academia and industry. Testing technology plays a crucial role in ensuring the reliability and functionality of the product, and is a key area that requires breakthroughs in the development of chiplets and integrated chips. This paper offers a comprehensive overview of chiplet and integrated chip testing technologies, analyzing the current research status and challenges encountered in this critical field. In this paper, we first explore the testing process of integrated chips, including design for test (DfT), Known Good Die testing, integrated module testing, final testing, and system-level testing. The current research trends in integrated chip testing are reviewed, focusing on system-level DfT techniques and inter-chiplet interconnection testing methods. This article also introduces the testing equipment and fixtures required for integrated chip testing, as well as electronic design automation tools. Finally, the challenges and future directions faced by integrated chip testing technology are explored.
期刊介绍:
CJE focuses on the emerging fields of electronics, publishing innovative and transformative research papers. Most of the papers published in CJE are from universities and research institutes, presenting their innovative research results. Both theoretical and practical contributions are encouraged, and original research papers reporting novel solutions to the hot topics in electronics are strongly recommended.