Analysis of Thermal Stress Reliability of Inter-connect Structures in Stacked SiP Modules Under Thermal Cycling Loading

Abstract

With the rapidly growing demand for high density integrated circuits, advanced packaging technologies such as chip stacking and heterogeneous integration have become mainstream. However, reliability issues related to interconnect structures under thermal cycling loads have become increasingly prominent. This study systematically investigates the structural deformation of internal interconnects in stacked SiP modules caused by thermomechanical stress under temperature cycling conditions, with a specific focus on fatigue failure induced by thermal loads. Stress strain analyses are performed on both the upper and lower layers of bumps and the through silicon via (TSV) array to identify critical failure locations and predict thermal fatigue life. The results indicate that deformation is most severe at the corners of the stacked SiP module throughout the temperature cycling process, and these corner regions are also the most prone to failure for both bumps and TSVs. The bottom layer bumps experience higher stress than the top layer bumps and are thus more likely to suffer thermal fatigue failure. The critical failure nodes for the bumps are located at the contact interface between the upper surface of the corner bumps and the lower surface of the redistribution layer (RDL), with a predicted thermal fatigue life of 4.63 × 10⁴ cycles. For the TSV structures, the maximum equivalent stress of 226.41 MPa occurs at the corners of the interposer at the bottom of the stacked SiP module, corresponding to a predicted thermal fatigue life of 5.45 × 10⁶ cycles. In addition, increasing the bump height, reducing the bump pitch, and using SAC405 solder with a higher silver content are found to effectively enhance the thermal reliability of the bumps.