BlockPIM: Enabling Sparse LLM Inference on Dense PIM Architectures

IF 2 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
IEEE Computer Architecture Letters Pub Date : 2026-07-01 Epub Date: 2026-07-21 DOI:10.1109/LCA.2026.3715204
Seulki Kim;Yewon Jang;Yunhyeong Jeon;Kyeonghyeon Ryu;Daehoon Kim
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引用次数: 0

Abstract

Large Language Models (LLMs) have intensified the memory wall during inference, where performance is increasingly limited by memory bandwidth rather than computation. While Processing-In-Memory (PIM) and model compression techniques mitigate this issue, existing sparse PIM designs rely on CSR/COO formats that assume ultra-high sparsity (e.g., $> 90\%$), which is difficult to achieve in practical LLMs without significant accuracy loss. Moreover, fine-grained indexing introduces substantial metadata overhead, diminishing the benefits of pruning, especially under low-bit quantization. To address this mismatch, we propose BlockPIM, a PIM architecture that employs hardware-aligned coarse-grained pruning to efficiently execute sparse LLMs on standard dense computation units. BlockPIM replaces per-element indices with compact bitmaps and contiguous non-zero blocks, enabling sparse workloads to be processed directly on dense execution pipelines without complex index decoding or irregular control flow. Experimental results show that BlockPIM achieves up to 8.0× and 3.6× speedups over the NPU and state-of-the-art sparse PIM baselines, respectively, while reducing energy consumption by up to 95.2% and providing superior memory efficiency under practical accuracy constraints.
BlockPIM:在密集PIM架构上启用稀疏LLM推理
大型语言模型(llm)在推理过程中加强了内存墙,其性能越来越多地受到内存带宽而不是计算的限制。虽然内存中处理(PIM)和模型压缩技术缓解了这个问题,但现有的稀疏PIM设计依赖于CSR/COO格式,这些格式假设了超高的稀疏性(例如,90%),这在实际的llm中很难实现,而不会造成显著的准确性损失。此外,细粒度索引引入了大量的元数据开销,减少了修剪的好处,特别是在低比特量化下。为了解决这种不匹配,我们提出了BlockPIM,这是一种PIM架构,它采用硬件对齐的粗粒度修剪来有效地在标准密集计算单元上执行稀疏的llm。BlockPIM用紧凑的位图和连续的非零块取代了每个元素的索引,使得稀疏的工作负载可以直接在密集的执行管道上处理,而不需要复杂的索引解码或不规则的控制流。实验结果表明,在NPU和最先进的稀疏PIM基线上,BlockPIM分别实现了高达8.0倍和3.6倍的加速,同时降低了高达95.2%的能耗,并在实际精度约束下提供了卓越的内存效率。
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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