Design of low power 9 T SRAM cell with high-performance decoder circuit using pass-transistor logic

Abstract

Electronic devices continue to be an essential component of many medical devices. These devices need Static Random Access Memory (SRAM) with power-efficient capabilities to process the data since they take up the majority of the die space. In particular, wearable technology is creating new design problems for integrated circuits (ICs), where static power dissipation and great low stability are critical requirements. This research proposes a new low-power 9 T SRAM cell design that enhances leakage power dissipation while preserving cell stability for low-power applications. An Enhanced Recycling Folded-Fully Differential Cascode Amplifier (ERFF-DCA) is incorporated into the peripheral circuits of RAM design to improve read speed and reduce overall power consumption. ERFF-DCA improves the performance in SRAM by recycling current within the amplifier, using high-speed current mirrors for phase margin improvement, and associating cross-coupled local positive feedback to increase small and large constraints. Moreover, a Mixed-logic, Low-power, High-performance Decoder Circuit is employed to decrease leakage power and improve performance. The inclusion of a Pass-Transistor Logic Gate (PTLG) significantly enhances the stability of the memory by offering robust noise reduction and minimizing susceptibility to interferences. The proposed design’s efficiency is evaluated using the Cadence tool with 90 nm CMOS technology. The simulated outcomes are associated with current designs to verify the efficiency of the suggested design. The read and write power attained by the proposed model are 1.03E−05 nW and 1.01E−06 nW, which is expressively less than the current models.