Stochastic Framework for Extracting Worst Case Test Vectors in ASICs Under Single-Event Effects

Abstract

We present a stochastic framework for identifying worst-case test vectors (WCTVs) that maximize the single-event transient (SET) vulnerability in application-specific integrated circuits (ASICs). The proposed approach integrates cell-level SET sensitivity modeling with probabilistic transfer matrices (PTMs) and a novel Euclidean-norm error metric to systematically evaluate thousands of candidate vectors derived from industry-standard test suites. For each test vector, stimulus probabilities are propagated through gate-level netlists (based on XFAB XH018 technology) to quantify primary-output perturbations relative to error-free baselines. The framework has been rigorously validated using Cadence Virtuoso transient simulations on ISCAS’85 benchmark circuits. Results show that the proposed methodology achieves accuracy comparable to transistor-level simulation while reducing computational cost by several orders of magnitude. In addition, the automated flow ensures scalability to complex ASIC designs. Results demonstrate that WCTVs induce $2.2\times $ more errors (SET-sensitive nodes) than random vectors, leading to a 56% reduction in conservative mean time between failures (MTBFs) estimates, highlighting the necessity of worst-case analysis for radiation hardness assurance. We show that neglecting worst-case analysis leads to systematically overstated reliability projections in radiation environments, highlighting the necessity of WCTV-based hardness assurance for mission-critical ASICs.