{"title":"SoftmaxPIM: An HBM-Based PIM Architecture for Accelerating GeMV–Softmax Execution Pipeline","authors":"Taewoon Kang;Namhun Kim;Jihun Lee;Murali Annavaram;Gunjae Koo","doi":"10.1109/LCA.2026.3716671","DOIUrl":null,"url":null,"abstract":"LLM inference is dominated by GeMV and softmax computations during attention. These computations impose substantial compute and memory bandwidth demands. Prior works have demonstrated that HBM-based PIM architectures effectively accelerate GeMV. However, softmax remains a critical bottleneck due to frequent data movement. In this work, we make the case for computing softmax operations in memory and integrate them with in-memory GeMV operations to provide a comprehensive in-memory LLM accelerator engine. We propose SoftmaxPIM, an in-HBM compute architecture that tightly integrates GeMV with a lightweight near-bank softmax unit. The proposed softmax unit employs an approximation-based softmax formulation that removes reduction operations, enabling the entire GeMV–softmax pipeline to execute within the HBM memory stack. By eliminating host-memory transfers, the proposed design significantly reduces softmax latency. Our simulation results demonstrate up to 42.7× speedup over a CPU and 2.64× over an RTX3090 GPU, as well as up to 1.45× improvement over the prior in-memory attention accelerator AttAcc.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 2","pages":"287-290"},"PeriodicalIF":2.0000,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Computer Architecture Letters","FirstCategoryId":"94","ListUrlMain":"https://ieeexplore.ieee.org/document/11622666/","RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"2026/7/23 0:00:00","PubModel":"Epub","JCR":"Q4","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
LLM inference is dominated by GeMV and softmax computations during attention. These computations impose substantial compute and memory bandwidth demands. Prior works have demonstrated that HBM-based PIM architectures effectively accelerate GeMV. However, softmax remains a critical bottleneck due to frequent data movement. In this work, we make the case for computing softmax operations in memory and integrate them with in-memory GeMV operations to provide a comprehensive in-memory LLM accelerator engine. We propose SoftmaxPIM, an in-HBM compute architecture that tightly integrates GeMV with a lightweight near-bank softmax unit. The proposed softmax unit employs an approximation-based softmax formulation that removes reduction operations, enabling the entire GeMV–softmax pipeline to execute within the HBM memory stack. By eliminating host-memory transfers, the proposed design significantly reduces softmax latency. Our simulation results demonstrate up to 42.7× speedup over a CPU and 2.64× over an RTX3090 GPU, as well as up to 1.45× improvement over the prior in-memory attention accelerator AttAcc.
期刊介绍:
IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.