Clover: Storage-Efficient Page Table Replication in Wafer-Scale GPUs

IF 2 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
IEEE Computer Architecture Letters Pub Date : 2026-07-01 Epub Date: 2026-07-29 DOI:10.1109/LCA.2026.3718473
Sungbin Jang;Yongho Lee;Seokin Hong
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引用次数: 0

Abstract

Wafer-scale GPUs integrate many GPU modules (GPMs) on a single wafer, but their distributed organization makes the address translation non-uniform: on an L2 TLB miss, a page table walker may fetch a leaf-level PTE from a remote GPM across the on-wafer mesh. Across 16 irregular applications, ideal full replication reduces execution time by 54.9% but requires $36\times$ of the storage of an unreplicated page table in a 6 × 6 mesh topology, equivalent to approximately 7.2% of the mapped memory footprint with 4KB pages. To this end, we propose Clover, a storage-efficient page-table replication mechanism that partitions the page table and applies a topology-aware $k$-hop placement. It allows every GPM to reach any partition within a small bounded number of hops while preserving conventional page-walk logic and keeping replicas coherent at low traffic. Clover reduces execution time by 44.9% on average while reducing aggregate page-table storage from $36\times$ to $7.2\times$ the unreplicated page-table size.
Clover:在晶圆级gpu中的高效存储页表复制
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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