Agentic LLMs for Microarchitecture Research: The Role of the Human Architect

IF 2 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
IEEE Computer Architecture Letters Pub Date : 2026-07-01 Epub Date: 2026-07-30 DOI:10.1109/LCA.2026.3718795
Georgios Vavouliotis
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引用次数: 0

Abstract

Agentic Large Language Models (LLMs) are rapidly becoming an important tool for architecture research, raising a concrete question for the computer architecture community: can an architect simply ask an agent to design a novel mechanism with a better score (e.g., IPC) and expect a meaningful answer? In this work, we study two modes of agentic use on the same microarchitectural domain with the same agentic model: unguided, in which the agent receives a problem statement, a curated seed library, a scoring function, and constraints, and guided, in which a human domain expert additionally reviews iterations and redirects the search when it stalls or drifts. Our evaluation shows that the unguided agent produces a design that performs close to, but below, the state-of-the-art, while the guided agentic design outperforms it. From this contrast, we distill a practical recipe for using today’s agents in microarchitecture research: they are most effective not as autonomous architects but as high-throughput collaborators whose output improves substantially under a human architect’s steering.
微建筑研究代理法学硕士:人类建筑师的角色
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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