VLSI and FPGA implementation of high-speed Vedic MAC architecture using Han Carlson adder

Abstract

The capacity of processors to withstand the problems that arise from integrating CPU cores in a single IC is an ongoing requirement for digital signal processors (DSP). DSP is utilized for many processes such as convolution, transformation, correlation, and filtering. These processes entail multiplication, and successive additions impact the execution time and arrangement performance. Thus, multiplying and accumulating units (MAC) is essential in DSP. The MAC unit is focused on high-performance processes. Finally, DSP algorithms rely heavily on the MAC’s performance. The functionality of the proposed methods is tested using a Kintex, Artix, and Virtex Field Programmable Gate Array (FPGA) in Xilinx Vivado 2022.2 and ASIC 45 nm technology. Following a thorough investigation, we determined that the Urdhva-tiryagbhyam Vedic multiplication (UVM) technique with Pipelining(P) performed better than other multipliers. The present investigation describes the development of a high-speed MAC unit for arithmetic applications that use a high-speed pipelined Vedic multiplier (VM). The MAC unit’s VM and adder blocks are constructed using the Han Carlson adder (HCA). The proposed PUVMHCA provides considerable delay reductions of 43%, 62.14%, 70.02%, and 78.64% for various bit widths. The MAC-PUVMHCA design reduces delay by 63.55% and improves area by 19.25% for 32-bit FPGA implementations.