A 7.33 nW Ratio Wake-Up Timer With XO and Auxiliary Oscillator for Real-Time Shock Recovery

IF 3.2 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Ehab A. Hamed;Inhee Lee
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引用次数: 0

Abstract

Precision timing is a fundamental requirement for ultralow-power Internet-of-Things (IoT) nodes, wildlife trackers, and wearable health devices. However, maintaining accuracy in these severely power-constrained systems is difficult due to the mechanical shock sensitivity of crystal oscillators (XOs). This work proposes a ratio wake-up timer (Ratio-WUT) designed to enhance XO shock resilience with very low power overhead. The system integrates a 5.58 nW XO with a secondary ultralow-power auxiliary oscillator (AuxO). A 1.75 nW digital controller actively monitors the ratio between XO and AuxO cycles, triggering an autonomous restart sequence immediately upon detecting an XO failure. Unlike conventional hybrid timers that rely on periodic wake-up checks, the Ratio-WUT provides continuous, real-time fault detection and correction. The prototype features a custom 180 nm CMOS XO and subthreshold AuxO, with control logic validated on an FPGA. Detailed postlayout analysis of a fully integrated version estimates a total power consumption of 7.33 nW. Experimental validation confirms the system’s ability to recover from mechanical shock events in real-time while maintaining wake-up functionality. By leveraging the inherent stability of the XO for timing while using the AuxO for supervision, the Ratio-WUT achieves a $3.85\times $ power reduction compared to prior hybrid architectures.
具有XO和辅助振荡器的7.33 nW比唤醒定时器,用于实时冲击恢复
精确计时是超低功耗物联网(IoT)节点、野生动物追踪器和可穿戴健康设备的基本要求。然而,由于晶体振荡器(xo)的机械冲击敏感性,在这些功率严重受限的系统中保持精度是困难的。这项工作提出了一种比率唤醒定时器(ratio - wut),旨在以非常低的功耗开销增强XO冲击弹性。该系统集成了一个5.58 nW XO和一个次级超低功率辅助振荡器(AuxO)。一个1.75 nW的数字控制器主动监控XO和AuxO周期之间的比率,在检测到XO故障后立即触发自动重启序列。与依赖定期唤醒检查的传统混合计时器不同,Ratio-WUT提供连续、实时的故障检测和纠正。该原型具有定制的180 nm CMOS XO和亚阈值AuxO,并在FPGA上验证了控制逻辑。全面集成版本的详细布局后分析估计总功耗为7.33 nW。实验验证证实了该系统能够从机械冲击事件中实时恢复,同时保持唤醒功能。通过利用XO计时的固有稳定性,同时使用AuxO进行监督,Ratio-WUT与之前的混合架构相比,功耗降低了3.85美元。
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来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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