{"title":"A 7.33 nW Ratio Wake-Up Timer With XO and Auxiliary Oscillator for Real-Time Shock Recovery","authors":"Ehab A. Hamed;Inhee Lee","doi":"10.1109/TVLSI.2026.3695454","DOIUrl":null,"url":null,"abstract":"Precision timing is a fundamental requirement for ultralow-power Internet-of-Things (IoT) nodes, wildlife trackers, and wearable health devices. However, maintaining accuracy in these severely power-constrained systems is difficult due to the mechanical shock sensitivity of crystal oscillators (XOs). This work proposes a ratio wake-up timer (Ratio-WUT) designed to enhance XO shock resilience with very low power overhead. The system integrates a 5.58 nW XO with a secondary ultralow-power auxiliary oscillator (AuxO). A 1.75 nW digital controller actively monitors the ratio between XO and AuxO cycles, triggering an autonomous restart sequence immediately upon detecting an XO failure. Unlike conventional hybrid timers that rely on periodic wake-up checks, the Ratio-WUT provides continuous, real-time fault detection and correction. The prototype features a custom 180 nm CMOS XO and subthreshold AuxO, with control logic validated on an FPGA. Detailed postlayout analysis of a fully integrated version estimates a total power consumption of 7.33 nW. Experimental validation confirms the system’s ability to recover from mechanical shock events in real-time while maintaining wake-up functionality. By leveraging the inherent stability of the XO for timing while using the AuxO for supervision, the Ratio-WUT achieves a <inline-formula> <tex-math>$3.85\\times $ </tex-math></inline-formula> power reduction compared to prior hybrid architectures.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 8","pages":"2681-2685"},"PeriodicalIF":3.2000,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11543517/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"2026/6/2 0:00:00","PubModel":"Epub","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
Precision timing is a fundamental requirement for ultralow-power Internet-of-Things (IoT) nodes, wildlife trackers, and wearable health devices. However, maintaining accuracy in these severely power-constrained systems is difficult due to the mechanical shock sensitivity of crystal oscillators (XOs). This work proposes a ratio wake-up timer (Ratio-WUT) designed to enhance XO shock resilience with very low power overhead. The system integrates a 5.58 nW XO with a secondary ultralow-power auxiliary oscillator (AuxO). A 1.75 nW digital controller actively monitors the ratio between XO and AuxO cycles, triggering an autonomous restart sequence immediately upon detecting an XO failure. Unlike conventional hybrid timers that rely on periodic wake-up checks, the Ratio-WUT provides continuous, real-time fault detection and correction. The prototype features a custom 180 nm CMOS XO and subthreshold AuxO, with control logic validated on an FPGA. Detailed postlayout analysis of a fully integrated version estimates a total power consumption of 7.33 nW. Experimental validation confirms the system’s ability to recover from mechanical shock events in real-time while maintaining wake-up functionality. By leveraging the inherent stability of the XO for timing while using the AuxO for supervision, the Ratio-WUT achieves a $3.85\times $ power reduction compared to prior hybrid architectures.
期刊介绍:
The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society.
Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.
To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.