RAW-PM: Reliability-Aware Weighted Polar Mapping for Hard-Decision Decoding in 3-D NAND Flash Memory

IF 3.2 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Debao Wei;Huqi Xiang;Dixin Ma;Yongchao Wang;Liyan Qiao
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引用次数: 0

Abstract

As 3-D nand flash memory continues to scale toward higher density, significant reliability disparities arise among different pages in triple-level cell (TLC) flash, posing severe challenges to error-correction codes (ECCs) in the middle and late stages of flash lifetime. Polar codes have been introduced into flash storage systems due to their near-capacity performance; however, their decoding heavily relies on the accuracy of log-likelihood ratios (LLRs). Hard-decision sensing in flash memory leads to severe loss of soft information, thereby limiting the achievable error-correction performance. To address these challenges, this article proposes a page-aware reliability optimization scheme for polar codes in 3-D TLC flash memory. First, a page-aware polar bit mapping (PA-PBM) scheme is proposed, which exploits the mismatch between polar bit importance and page reliability by mapping critical bits to highly reliable pages and frozen bits to less reliable pages, thereby reducing the probability of critical errors. Building upon PA-PBM, a reliability-aware weighted polar mapping (RAW-PM) scheme is further developed, which incorporates page-level raw bit error rate (RBER) information to construct confidence-differentiated pseudo-soft LLRs and refines the bit mapping strategy, enabling weighted path metric (PM) correction and improving decoding accuracy under hard-decision sensing. Extensive experiments are conducted on a flash memory test platform to evaluate the proposed schemes. The results demonstrate that RAW-PM significantly improves the frame error-correction success rate in the middle and late stages of flash lifetime and reduces the post-ECC uncorrectable bit error rate (UBER) by more than one order of magnitude. Under typical large-scale access, RAW-PM introduces no additional read operations, requires no changes to the decoder architecture, and achieves these gains with minimal control and computational overhead, demonstrating excellent practical feasibility.
3-D NAND闪存硬决策解码的可靠性感知加权极坐标映射
随着3-D nand闪存不断向高密度方向发展,三层单元(TLC)闪存的不同页之间出现了显著的可靠性差异,对闪存寿命中后期的纠错码(ecc)提出了严峻的挑战。由于其接近容量的性能,Polar码已被引入闪存存储系统;然而,它们的解码在很大程度上依赖于对数似然比(llr)的准确性。闪存中的硬决策传感导致软信息的严重丢失,从而限制了可实现的纠错性能。为了解决这些问题,本文提出了一种三维TLC闪存极性码的页面感知可靠性优化方案。首先,提出了一种页面感知的极性位映射(PA-PBM)方案,该方案利用极性位重要性与页面可靠性之间的不匹配,将关键位映射到高可靠的页面,将冻结位映射到不可靠的页面,从而降低临界错误的概率。在PA-PBM的基础上,进一步提出了一种可靠性感知加权极坐标映射(raw -PM)方案,该方案结合页面级原始误码率(RBER)信息构建置信度差异的伪软llr,并对位映射策略进行了改进,实现了加权路径度量(PM)校正,提高了硬决策感知下的译码精度。在闪存测试平台上进行了大量的实验来评估所提出的方案。结果表明,RAW-PM显著提高了flash生命周期中后期的帧纠错成功率,并将ecc后不可纠错误码率(UBER)降低了一个数量级以上。在典型的大规模访问下,RAW-PM不引入额外的读取操作,不需要更改解码器架构,并且以最小的控制和计算开销实现这些增益,展示了出色的实际可行性。
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来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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