{"title":"RAW-PM: Reliability-Aware Weighted Polar Mapping for Hard-Decision Decoding in 3-D NAND Flash Memory","authors":"Debao Wei;Huqi Xiang;Dixin Ma;Yongchao Wang;Liyan Qiao","doi":"10.1109/TVLSI.2026.3687257","DOIUrl":null,"url":null,"abstract":"As 3-D <sc>nand</small> flash memory continues to scale toward higher density, significant reliability disparities arise among different pages in triple-level cell (TLC) flash, posing severe challenges to error-correction codes (ECCs) in the middle and late stages of flash lifetime. Polar codes have been introduced into flash storage systems due to their near-capacity performance; however, their decoding heavily relies on the accuracy of log-likelihood ratios (LLRs). Hard-decision sensing in flash memory leads to severe loss of soft information, thereby limiting the achievable error-correction performance. To address these challenges, this article proposes a page-aware reliability optimization scheme for polar codes in 3-D TLC flash memory. First, a page-aware polar bit mapping (PA-PBM) scheme is proposed, which exploits the mismatch between polar bit importance and page reliability by mapping critical bits to highly reliable pages and frozen bits to less reliable pages, thereby reducing the probability of critical errors. Building upon PA-PBM, a reliability-aware weighted polar mapping (RAW-PM) scheme is further developed, which incorporates page-level raw bit error rate (RBER) information to construct confidence-differentiated pseudo-soft LLRs and refines the bit mapping strategy, enabling weighted path metric (PM) correction and improving decoding accuracy under hard-decision sensing. Extensive experiments are conducted on a flash memory test platform to evaluate the proposed schemes. The results demonstrate that RAW-PM significantly improves the frame error-correction success rate in the middle and late stages of flash lifetime and reduces the post-ECC uncorrectable bit error rate (UBER) by more than one order of magnitude. Under typical large-scale access, RAW-PM introduces no additional read operations, requires no changes to the decoder architecture, and achieves these gains with minimal control and computational overhead, demonstrating excellent practical feasibility.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 7","pages":"2165-2175"},"PeriodicalIF":3.2000,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11513844/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"2026/3/11 0:00:00","PubModel":"Epub","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
As 3-D nand flash memory continues to scale toward higher density, significant reliability disparities arise among different pages in triple-level cell (TLC) flash, posing severe challenges to error-correction codes (ECCs) in the middle and late stages of flash lifetime. Polar codes have been introduced into flash storage systems due to their near-capacity performance; however, their decoding heavily relies on the accuracy of log-likelihood ratios (LLRs). Hard-decision sensing in flash memory leads to severe loss of soft information, thereby limiting the achievable error-correction performance. To address these challenges, this article proposes a page-aware reliability optimization scheme for polar codes in 3-D TLC flash memory. First, a page-aware polar bit mapping (PA-PBM) scheme is proposed, which exploits the mismatch between polar bit importance and page reliability by mapping critical bits to highly reliable pages and frozen bits to less reliable pages, thereby reducing the probability of critical errors. Building upon PA-PBM, a reliability-aware weighted polar mapping (RAW-PM) scheme is further developed, which incorporates page-level raw bit error rate (RBER) information to construct confidence-differentiated pseudo-soft LLRs and refines the bit mapping strategy, enabling weighted path metric (PM) correction and improving decoding accuracy under hard-decision sensing. Extensive experiments are conducted on a flash memory test platform to evaluate the proposed schemes. The results demonstrate that RAW-PM significantly improves the frame error-correction success rate in the middle and late stages of flash lifetime and reduces the post-ECC uncorrectable bit error rate (UBER) by more than one order of magnitude. Under typical large-scale access, RAW-PM introduces no additional read operations, requires no changes to the decoder architecture, and achieves these gains with minimal control and computational overhead, demonstrating excellent practical feasibility.
期刊介绍:
The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society.
Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.
To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.