{"title":"Bayesian Model Calibration for Deep-Learning-Based Indirect Test of Analog Circuits","authors":"Jiaming Zhao;Yijiu Zhao;Shibo Chen;Jiawei Cao;Naixin Zhou;E. Shao","doi":"10.1109/TVLSI.2026.3680902","DOIUrl":null,"url":null,"abstract":"The indirect test offers a cost-effective alternative for the specification test of analog integrated circuits (ICs). It infers high-cost specifications from low-cost measurements through a mapping function. Deep learning provides an efficient means for modeling this mapping. However, batch-to-batch variations in IC manufacturing often lead to distribution shifts, which degrade the accuracy of such data-driven techniques. To address this, we propose a transfer learning-based framework—Bayesian model calibration (BMC)—for the indirect test. During testing, a deep neural network (DNN) is trained with early data for estimation. When a new-batch arrives, a small number of samples are conventionally tested to form a calibration set. The original estimator is updated with the new dataset via a Bayesian loss function. This loss function integrates a prior term (reflecting the early data) and a likelihood term (reflecting the new data), enabling a principled tradeoff between prior knowledge and new observations. The estimator thereby adapts its parameters to improve accuracy on the new batch. Moreover, by adjusting the relative weights of the prior and likelihood terms, the extent of model update can be controlled to match the degree of distribution shift, achieving optimal calibration. The proposed approach is evaluated on a simulated operational amplifier and two commercial IC datasets to demonstrate its advantage. The BMC can improve accuracy on new batches with minimal additional samples. Moreover, by flexibly integrating the prior knowledge and new data, it outperforms baseline methods such as direct data combination (DC) and simple fine-tuning (SFT).","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 7","pages":"2274-2283"},"PeriodicalIF":3.2000,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11478736/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"2026/4/10 0:00:00","PubModel":"Epub","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
The indirect test offers a cost-effective alternative for the specification test of analog integrated circuits (ICs). It infers high-cost specifications from low-cost measurements through a mapping function. Deep learning provides an efficient means for modeling this mapping. However, batch-to-batch variations in IC manufacturing often lead to distribution shifts, which degrade the accuracy of such data-driven techniques. To address this, we propose a transfer learning-based framework—Bayesian model calibration (BMC)—for the indirect test. During testing, a deep neural network (DNN) is trained with early data for estimation. When a new-batch arrives, a small number of samples are conventionally tested to form a calibration set. The original estimator is updated with the new dataset via a Bayesian loss function. This loss function integrates a prior term (reflecting the early data) and a likelihood term (reflecting the new data), enabling a principled tradeoff between prior knowledge and new observations. The estimator thereby adapts its parameters to improve accuracy on the new batch. Moreover, by adjusting the relative weights of the prior and likelihood terms, the extent of model update can be controlled to match the degree of distribution shift, achieving optimal calibration. The proposed approach is evaluated on a simulated operational amplifier and two commercial IC datasets to demonstrate its advantage. The BMC can improve accuracy on new batches with minimal additional samples. Moreover, by flexibly integrating the prior knowledge and new data, it outperforms baseline methods such as direct data combination (DC) and simple fine-tuning (SFT).
期刊介绍:
The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society.
Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.
To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.