RLRM: Reinforcement Learning-Based Routing for Ring-Augmented Mesh NoC

IF 3.2 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Juan Fang;Jingming Guo;Yubin He;Qi Ming
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引用次数: 0

Abstract

Modern multicore processors increasingly rely on network-on-chip (NoC) architectures to support high-bandwidth and low-latency communication. Traditional mesh-based NoC topologies suffer from uneven load distribution, with central router nodes frequently becoming congestion hot spots. The existing approaches mainly focus on introducing bypass links or independent ring interconnects. However, bypass links can only alleviate congestion between fixed routers, and routers not included in the ring still rely on conventional mesh forwarding, limiting the overall performance improvement. To address these challenges, this article proposes a reinforcement learning-based routing for ring-augmented mesh NoC (RLRM) to improve communication efficiency in multicore processors. First, we design a ring-augmented $8\times 8$ mesh topology that integrates horizontal and vertical ring interconnects to achieve balanced load distribution and mitigate congestion hotspots. Second, we equip each router with a topology-aware reinforcement learning (RL) agent that dynamically selects paths based on congestion conditions, thereby proactively avoiding performance bottlenecks. Extensive experiments demonstrate that the proposed solution provides a scalable and efficient architecture for high-performance computing and multicore NoC systems. Experimental results under realistic benchmark traffic patterns show that RLRM reduces average latency by 22.78% compared to conventional mesh and static hybrid routing schemes.
基于强化学习的环增强网格NoC路由
现代多核处理器越来越依赖于片上网络(NoC)架构来支持高带宽和低延迟通信。传统的基于网格的NoC拓扑存在负载分布不均匀的问题,中心路由器节点经常成为拥塞热点。现有的方法主要集中在引入旁路链路或独立环形互连。但是,bypass链路只能缓解固定路由器之间的拥塞,不在环内的路由器仍然依赖传统的网状转发,限制了整体性能的提升。为了解决这些挑战,本文提出了一种基于强化学习的环增强网格NoC (RLRM)路由,以提高多核处理器中的通信效率。首先,我们设计了一个环增强的$8\ × 8$网状拓扑,该拓扑集成了水平和垂直环互连,以实现均衡负载分配并缓解拥塞热点。其次,我们为每个路由器配备了一个拓扑感知强化学习(RL)代理,该代理可以根据拥塞情况动态选择路径,从而主动避免性能瓶颈。大量的实验表明,该方案为高性能计算和多核NoC系统提供了可扩展和高效的架构。在真实基准流量模式下的实验结果表明,与传统的网状路由和静态混合路由相比,RLRM的平均延迟降低了22.78%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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