DayPQ: Dynamic Layerwise Pruning and Quantization for LLM Inference Acceleration

IF 3.2 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Yongchao Xu;Mingxuan Li;Ziying Zhuo;Qinzhe Zhi;Tianyu Jia;Meiqi Wang
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引用次数: 0

Abstract

The deployment of the prevailing large language models (LLMs) on resource-constrained hardware faces critical challenges due to their massive computational and memory requirements. Pruning and quantization (PQ), as two predominant techniques for LLM acceleration, face the challenge of fully preserving model capabilities while achieving significant acceleration in practice. Static PQ irreversibly discards potentially critical parameters and degrades precision across diverse inputs, which must be compensated through fine-tuning. Dynamic PQ preserves accuracy but incurs prohibitive hardware overhead and additional latency from runtime adaptations. Achieving low-latency and overhead-efficient dynamic PQ requires the co-design of adaptive compression tightly integrated with hardware. In this work, we present DayPQ, an algorithm-hardware co-optimization technique for efficient LLM inference: self-adaptive norm-based pruning and bias-shifting FP8 quantization at the algorithm level, synergized with a multiplication-free shift–add PE array and switchable dataflow at the hardware level, achieving dynamic acceleration with the negligible accuracy loss and zero additional latency. DayPQ enables adaptive PQ by intrinsically exploiting normalization operations from the model’s inference process instead of extra operations. Simultaneously, it establishes dynamic orthogonality between sparsity and quantization, where these dual compression mechanisms synergistically enhance the redundancy reduction beyond mere additive effects of independent operations. Our evaluation shows that DayPQ obtains an average $3.13\times $ higher energy efficiency and $2.03\times $ performance boost than three state-of-the-art (SOTA) accelerators.
LLM推理加速的动态分层剪枝和量化
由于大量的计算和内存需求,在资源受限的硬件上部署流行的大型语言模型面临着严峻的挑战。修剪和量化(PQ)作为LLM加速的两种主要技术,在实践中面临着在实现显著加速的同时完全保留模型功能的挑战。静态PQ不可逆转地丢弃了潜在的关键参数,并降低了不同输入的精度,这必须通过微调来补偿。动态PQ保持了准确性,但会带来令人望而却步的硬件开销和运行时适应带来的额外延迟。实现低延迟和开销高效的动态PQ需要与硬件紧密集成的自适应压缩协同设计。在这项工作中,我们提出了DayPQ,一种用于高效LLM推理的算法-硬件协同优化技术:在算法层面上,基于自适应范数的修剪和偏置移位FP8量化,在硬件层面上,与无乘法移位-添加PE阵列和可切换的数据流协同,在可忽略的精度损失和零额外延迟的情况下实现动态加速。DayPQ通过内在地利用模型推理过程中的规范化操作而不是额外的操作来实现自适应PQ。同时,它建立了稀疏性和量化之间的动态正交性,其中这些双重压缩机制协同增强了冗余减少,而不仅仅是独立操作的相加效应。我们的评估表明,DayPQ获得了比三个最先进的(SOTA)加速器平均高3.13美元的能源效率和2.03美元的性能提升。
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来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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