{"title":"JADE: Joint Architecture-Dataflow Exploration for LLM Inference on Heterogeneous In- and Near-Memory Computing Systems","authors":"Yimin Wang;Zhen Wu;Yue Jiet Chong;Xuanyao Fong","doi":"10.1109/JETCAS.2026.3679018","DOIUrl":null,"url":null,"abstract":"Large Language Model (LLM) inference challenges memory/computing organization and dataflow optimization on traditional hardware stacks due to its various attention mechanisms and autoregressive structure. In-memory computing (IMC) and near-memory computing (NMC) architectures have emerged as potential solutions to reduce the memory burden in LLMs. However, efficient LLM orchestration on IMC/NMC, as well as dedicated IMC/NMC architecture optimization, are interrelated, encompassing a hardware-software co-design space of a myriad of parameters, which still remains largely underexplored. This work provides a joint architecture-dataflow exploration (JADE) framework that covers both architectural factors on computing/memory/communication, and algorithmic factors on LLM dataflow. We identify key configurations in four categories: computing and memory organization, interconnection topology, matrix multiplication (MM) unrolling and mapping, and attention mechanism. A unified MM representation enables flexible unrolling and mapping on various architectural organizations. Dataflow is routed based on the collective communication patterns inherent in the distributed LLMs and the features of common topologies. Finally, case studies show the design tradeoffs between key design options and provide insights into both homogeneous and heterogeneous IMC/NMC design for LLMs.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 2","pages":"378-388"},"PeriodicalIF":3.8000,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11457955/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"2026/3/30 0:00:00","PubModel":"Epub","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
Large Language Model (LLM) inference challenges memory/computing organization and dataflow optimization on traditional hardware stacks due to its various attention mechanisms and autoregressive structure. In-memory computing (IMC) and near-memory computing (NMC) architectures have emerged as potential solutions to reduce the memory burden in LLMs. However, efficient LLM orchestration on IMC/NMC, as well as dedicated IMC/NMC architecture optimization, are interrelated, encompassing a hardware-software co-design space of a myriad of parameters, which still remains largely underexplored. This work provides a joint architecture-dataflow exploration (JADE) framework that covers both architectural factors on computing/memory/communication, and algorithmic factors on LLM dataflow. We identify key configurations in four categories: computing and memory organization, interconnection topology, matrix multiplication (MM) unrolling and mapping, and attention mechanism. A unified MM representation enables flexible unrolling and mapping on various architectural organizations. Dataflow is routed based on the collective communication patterns inherent in the distributed LLMs and the features of common topologies. Finally, case studies show the design tradeoffs between key design options and provide insights into both homogeneous and heterogeneous IMC/NMC design for LLMs.
期刊介绍:
The IEEE Journal on Emerging and Selected Topics in Circuits and Systems is published quarterly and solicits, with particular emphasis on emerging areas, special issues on topics that cover the entire scope of the IEEE Circuits and Systems (CAS) Society, namely the theory, analysis, design, tools, and implementation of circuits and systems, spanning their theoretical foundations, applications, and architectures for signal and information processing.