A CMOS Compatible Energy Efficient 6T NV-SRAM-Based Accelerator Employing Binary Neural Networks in 22 nm FDSOI Technology

Abstract

In this paper, a CMOS compatible non-volatile 6T-SRAM (NV-SRAM) based accelerator is proposed using a Compute-In-Memory (CIM) and Binary Neural Network (BNN) architecture to scale the persistent and energy-efficient on-chip storage for Edge AI systems. The proposed NV-SRAM facilitate reliable on-chip storage for weights and feature maps without off-chip reloading, providing data persistence and security as well as reducing information lost. As a case study, the proposed accelerator utilizes a ( $400\times 200$ ) NV-SRAM array to enable binarized $20\times 20$ MNIST image processing and efficient mapping of 400-bit activation vectors with the assistance of the specially designed peripheral circuits. Especially, on-chip in-memory XNOR and pop-count operations reduce inter-chip data movement, and as a result, lead to an energy-efficient processing. The design is implemented and validated in 22 nm FDSOI Technology with 0.8 V power supply to achieve throughput: 8 TOPS (8000 GOPS) and 200 TOPS/W and inference accuracy: 96.85% with MLP for MNIST, showing high energy efficiency, scalable parallelism, and small silicon area. As compared to state-of-the-art, the proposed NV-SRAM based BNN accelerator combines non-volatility, high computational throughput, and CMOS compatibility, making it a strong candidate for Internet of Things (IoT), robotics, autonomous sensors, and embedded vision in Edge AI platforms.