NoiseGuard: A Comprehensive Framework With Noise Modeling, Noise-Aware Training, and Noise Compensation for In-Memory Computing SoC

Abstract

Despite the tremendous potential of in-memory computing (IMC) for AI applications, analog IMC still faces critical challenges related to noise sensitivity and computational accuracy, largely due to intrinsic nonidealities. These limitations significantly restrict the scalability and real-world deployability of analog IMC systems. To address accuracy degradation caused by hardware noise, we propose a comprehensive framework integrating noise modeling, noise-aware training (NAT), and hardware-adaptive compensation (HAC). Specifically, a noise model is derived from empirical measurements of a 40-nm eFlash-based IMC system-on-chip (SoC) to capture diverse noise sources. The NAT scheme embeds the noise model into the training pipeline to enhance algorithm robustness, while the noise model guides HAC to mitigate the effects of device- and circuit-level variations during inference. The experimental results demonstrate that the noise model achieves a cosine similarity above 0.99 with actual chip behavior. In a speech denoising task, NAT improves the perceptual evaluation of speech quality (PESQ) by 0.168 (6.82%), while HAC reduces the output error variance by an average of 74.68%. Applied to multiple tasks including speech wake-up, speech denoising, and image super-resolution, our framework achieves improvements of 13.5% in wake-up accuracy, 0.7 (29.2%) in PESQ, and 2.82 dB (7.2%) in peak signal-to-noise ratio (PSNR), respectively. These results demonstrate the generality and effectiveness of the proposed framework across a range of AI tasks.