QuickCell: Fast Automatic Design of Standard Cells for Silicon Dangling Bond Logic

Abstract

In recent years, Silicon Dangling Bond (SiDB) logic has emerged as a promising beyond-CMOS technology due to its integration density and operating frequency. This advancement is driving the development of comprehensive design automation workflows, including physical simulators and gate design tools. Unlike conventional circuit technology, where logic is implemented through transistors, SiDB logic utilizes quantum dots with variable charge states. By strategically arranging these dots, standard logic functions like or, and, nand, and so on can be implemented, which are usually provided as standard cells in design processes. However, finding such arrangements that implement a given Boolean function is a tremendously complex task that involves considering numerous candidates and verifying them through computationally expensive physical simulation. Hence, the automatic obtainment of SiDB logic layouts is thus far limited to simple two-input functions only, which already require substantial computation resources. In contrast, conventional physical design algorithms for VLSI have long transitioned from single-gate considerations to multiinput standard cells. To address this challenge, this article proposes QuickCell, a fast algorithm for automatic standard cell design for SiDB logic that uses dedicated search space pruning techniques. In an extensive experimental evaluation, it is demonstrated that combining these pruning techniques yields: 1) a drastic reduction of the search space amounting to up to six orders of magnitude; 2) a corresponding decrease of the runtime by up to a factor of 91; 3) the capability to handle more complex functionality, as, for example, utilized in standard cells, for the first time, significantly narrowing the gap between SiDB logic and conventional CMOS design paradigms; and 4) a significant speedup compared to physical simulation (up to a factor of 10000), with near independence from the number of input–output (I/O) pins when determining the nonoperationality of a given layout. This efficiency makes these techniques—and by extension QuickCell—a powerful enabler for the design of complex standard cells.