RankTuner: When Design Tool Parameter Tuning Meets Preference Bayesian Optimization

IF 3.6 3区 计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Peng Xu;Su Zheng;Yuyang Ye;Chen Bai;Siyuan Xu;Hao Geng;Tsung-Yi Ho;Bei Yu
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引用次数: 0

Abstract

Electronic design automation (EDA) tools are critical in the very large scale integration (VLSI) flow. To address the challenges posed by the extensive search space and intricate feature interactions, statistical and machine learning methods have been employed. These methods aim to model tool parameters and treat the tuning process as a regression task. However, these regression-based methods suffer from inaccurate estimations owing to limited training samples. To address this issue, we propose a ranking-based tool parameter tuning framework, called RankTuner, which directly learns the dominant relationship between parameters. RankTuner utilizes a pairwise Gaussian process (GP) to estimate the probability and uncertainty of the dominance relationship. Our approach also integrates a Duel–Thompson sampling method to balance exploration and exploitation in parameter selections. A dimensionality reduction scheme with random embedding and trust region (TR) techniques is incorporated to enable parallel searches. Experimental results demonstrate the superiority of RankTuner compared to the cutting-edge tool parameter tuning methods.
RankTuner:当设计工具参数调优满足偏好贝叶斯优化时
电子设计自动化(EDA)工具在超大规模集成(VLSI)流程中至关重要。为了解决广泛的搜索空间和复杂的特征交互带来的挑战,采用了统计和机器学习方法。这些方法旨在对刀具参数进行建模,并将整定过程视为回归任务。然而,由于训练样本有限,这些基于回归的方法存在估计不准确的问题。为了解决这个问题,我们提出了一个基于排名的工具参数调优框架,称为RankTuner,它直接学习参数之间的主导关系。RankTuner利用两两高斯过程(GP)来估计优势关系的概率和不确定性。我们的方法还集成了Duel-Thompson采样方法,以平衡参数选择中的勘探和开发。采用随机嵌入和信任域(TR)技术的降维方案实现并行搜索。实验结果表明,RankTuner算法与现有的刀具参数调优方法相比具有一定的优越性。
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来源期刊
CiteScore
5.60
自引率
13.80%
发文量
500
审稿时长
7 months
期刊介绍: The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components. The aids include methods, models, algorithms, and man-machine interfaces for system-level, physical and logical design including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, hardware-software co-design and documentation of integrated circuit and system designs of all complexities. Design tools and techniques for evaluating and designing integrated circuits and systems for metrics such as performance, power, reliability, testability, and security are a focus.
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