URoute: Universal Routability Prediction

Abstract

Deep learning has emerged as the predominant technique for predicting routability in very-large-scale-integrated (VLSI) circuits. However, it often struggles to generalize to various tasks and performs poorly when addressing inherent data imbalance issues in electronic design automation (EDA). Overcoming these challenges typically requires retraining or fine-tuning models, which poses significant difficulties for chip engineers who lack resources and expertise in neural network training. In light of this, we propose and address the universal problem of routability prediction for the first time. By framing this issue as a meta-learning scenario, we propose a few-shot learning (FSL)-based approach, URoute, which adapts flexibly to new tasks by utilizing features of the query chip and labeled examples without additional training. To tackle the data imbalance problem, we further propose a meta-learning strategy based on importance sampling to optimize the model training process. To validate the generality and adaptability of URoute, we construct an FSL dataset based on CircuitNet and ISPD2015 datasets. Experimental results demonstrate that URoute exhibits greater robustness and flexibility compared to existing methods when handling unseen routability prediction tasks, achieving competitive results.