A Reliable ESD 3D-Integrated Design and Simulation (3D-IDS) Methodology for Wafer-on-Wafer Stacked DRAM

Abstract

The electrostatic discharge (ESD) protection design and verification methodology are particularly important for the wafer-on-wafer (WoW) stacked system due to the miniaturization of vertical interconnect cells, the simplification of vertical drivers, and the complexity of the 3D power network. This article introduces an ESD 3D-integrated design and simulation (3D-IDS) methodology for WoW 3D stacked DRAM, which incorporates customized ESD protection devices and vertical interconnect models, creating a comprehensive 3D ESD discharging network, addressing the challenges posed by high-density vertical connections in WoW 3D stacks. This 3D ESD network encompasses all crucial elements of 3D ESD discharging paths, including on-chip ESD protection devices and a comprehensive 3D power/ground discharge network. Silicon measurement results confirm that the ESD human body model (HBM) and charged device model (CDM) limitations corroborate the simulation forecasts. This validation confirms that the proposed ESD 3D-IDS methodology is a reliable and effective approach for ESD protection design and optimization in WoW stacked DRAM.