Single-Event Transient Analysis on NCringFET Devices and Inverter Circuits Utilizing Numerical Device Simulations

Abstract

The heavy ion radiation performance of NCringFET with single and dual-k spacers using both the inner and outer drain (OD) arrangements are investigated using 3-D technology computer aided design (TCAD) simulations. DC performance parameters, including on current ( ${I}_{\text {on}}$ ), off current ( ${I}_{\text {off}}$ ), and ${I}_{\text {on}}\big /{I}_{\text {off}}$ ratio, are obtained for all NCringFET structures. The behavior of NCringFET to heavy ion irradiation is analyzed, and the device’s susceptible area is identified via single-event transient (SET) analysis. It was discovered that the most susceptible area for an inner drain (ID) arrangement is the centre of the drain (CD), whereas the most susceptible area for an OD arrangement is the spacer near the drain (SND). The source region (CS) is the least susceptible area for both OD and ID arrangements. Also, the SET performance of NCringFET-based Inverters using both OD and ID arrangements are examined. NCringFET with an ID arrangement exhibits improved performance in radiation-prone areas due to its reduced collected charge, making it a more suitable choice for applications requiring high reliability and radiation tolerance at both the device level and circuit level.