A Subelectron-Noise Skipper-CCD Readout ASIC With Improved Channel-to-Channel Isolation and an Integrated Cryogenic Voltage Reference

Abstract

The multichannel integrating dual-slope noise-aware (MIDNA) application-specific integrated circuits (ASICs) are a series of skipper-CCD readout chips fabricated in a 65 nm low-power CMOS process that implement a correlated double sampling (CDS) signal processing chain based on dual-slope integrators. They are designed to operate from room temperature to cryogenic temperatures, down to 84 K. The present iteration of the ASIC has been fabricated with several design updates and the addition of an on-chip voltage reference, resulting in improved performance. This work presents the main vulnerabilities solved, the changes carried out, and the resulting performance benefits. Measurements with a skipper-CCD and the ASIC at 140 K showed that the single-electron resolution can be reached by averaging the measured charge in the analog domain using the analog pile-up technique with a readout noise as low as $\mathrm {0.11~e^{-}_{rms}}$ of equivalent charge for 1200 averaged samples. The channel-to-channel crosstalk was characterized, showing an improvement from −38 dB in the previous iteration to better than −62 dB in the present ASIC. When using the analog pile-up technique, one limiting factor was the residual offset after CDS. In the updated ASIC, improvements to the integrator offset have decreased the CDS residue from 3.2 to 0.2 mV, enabling additional signal pile-up.