A 20-Gb/s/pin 0.42-pJ/b Single-Ended Receiver With Ping-Pong Self-Referencing Technique

Abstract

This brief presents a 20-Gb/s/pin single-ended receiver (RX) utilizing a proposed ping-pong self-referencing (PPSR) technique. The prior self-referenced (SR) RXs suffer from a fundamental challenge in handling consecutive identical digits (CIDs), since their correction mechanism relies on detecting an unstable blind zone and requires complex digital overhead. The PPSR overcomes this by implementing two primary solutions. First, an analog CID-restoring feedback loop is integrated to actively secure a stable vertical margin even under long-term CID sequences. Second, the PPSR exploits the non-ideal low-pass filter (LPF) characteristic of the sample-and-hold (S&H) circuits. By intentionally adjusting the time constant ( $\tau _{\mathrm {SH}}$ ), a robust horizontal margin is achieved. Fabricated in 28 nm CMOS, the RX achieves a data rate of 20 Gb/s/pin while compensating–15 dB channel loss. The RX consumes 8.42 mW (0.42 pJ/bit) and demonstrates strong immunity to 100 MHz supply noise up to 200 mVpp.