Data Transfer Optimization for Loop Mapping on CGRAs via Polyhedral Transformation

Abstract

Coarse-grained reconfigurable arrays (CGRAs) play an important role in accelerating computation-intensive applications due to their flexibility and power efficiency. Most existing mapping works for CGRAs assume that all the data of a loop kernel can be previously moved from DRAM to scratchpad memory (SPM) with one data transfer. However, when targeting low-power CGRAs, the SPM can hardly hold the entire data, even for a small loop kernel, and it inevitably incurs multiple data transfers, leading to notable costs. In this case, where and how to perform data transfer, considering the DRAM access behavior, is crucial to the overall execution performance. To this end, this article proposes a data transfer optimization method to simultaneously optimize loop pipelining and data transfer. Since there is an interplay between loop structure and data transfer, we establish an optimization problem considering both polyhedral transformation and transfer strategy exploration, offering opportunities to find the near-optimal data transfer strategy within the search space. The experimental results show that compared with existing methods, our method can achieve $1.36\times -4.55\times $ speedup for loop kernels with different on-chip buffer sizes and only increases the compilation time by a small amount.