SALSy: Security-Aware Layout Synthesis

Abstract

Integrated circuits (ICs) are the target of diverse attacks during their lifetime. Fabrication-time attacks, such as the insertion of hardware Trojans (HTs), can give an adversary access to privileged data and/or the means to corrupt the IC’s internal computation. Postfabrication attacks, where the end-user takes a malicious role, also attempt to obtain privileged information through means such as fault injection and probing. Taking these threats into account, and at the same time, this article proposes a methodology for security-aware layout synthesis (SALSy), such that ICs can be designed with security in mind in the same manner as power–performance–area (PPA) metrics are considered today, a concept known as security closure. Furthermore, the tradeoffs between PPA and security are considered, and a chip is fabricated in a 65-nm CMOS commercial technology for validation purposes—a feature not seen in previous research on security closure. Measurements on the fabricated ICs indicate that SALSy promotes a modest increase in power to achieve significantly improved security metrics.