Approximate Logic Synthesis for Dot-Inverter Graphs Using Node Merging-Enhanced Genetic Algorithm-Based Approach

Abstract

This article presents a novel approach to approximate logic synthesis (ALS) targeting at Dot-Inverter Graph (DIG), which is known for its superior expressive ability among all three-input gates and its potential in the future technology. We focus on minimizing the size of DIG circuits while maintaining acceptable error rates (ERs) by introducing a node merging (NM)-enhanced genetic algorithm (GA)-based approach. The NM technique reduces the DIG size without altering its functionality, while the GA, incorporating average relative Hamming distance (ARHD) and a self-adjusted mutation level (ML), is used for ALS on DIGs. Our experimental results demonstrated that the proposed approach achieves a higher reduction rate and less CPU time on different sizes of circuits compared to the state-of-the-art ALS approach.