A 18.3–38.3-GHz Power Amplifier With Adaptive Dual-Voltage-Path Crossing Cold-FET Pair Achieving 22.7-dBm Psat and 31.9% PAE

Abstract

This brief presents a wideband linear CMOS power amplifier (PA) for 5G millimeter wave (mm-wave) applications. In order to improve linearity, this PA adopts an analog pre-distortion (APD) linearizer using an adaptive dual-voltage-path crossing cold-FET pair (ADCCP). The proposed ADCCP is implemented by connecting the drain and gate of differential cold-FET mutually in a crossing manner, which can enhance the equivalent impedance of cold-FET significantly. Moreover, an adaptive bias circuit (ABC) with dual-voltage-path is applied to control V_gs of ADCCP to transform the transistor from the saturation region to the turn-off region, which can further increase the equivalent impedance of the cold-FET to enhance linearity. In addition, input and interstage transformers are meticulously designed using gain shaping technique to ensure wideband performance. The implemented PA achieves a 3-dB bandwidth of 18.3-38.3 GHz, with the peak gain of 20.8 dB, peak saturated output power (P_sat) of 22.7 dBm, and peak power-added efficiency (PAE) of 31.9%. Wideband output power and efficiency performance was achieved with OP ${}_{\text {1dB}} \geq 21$ dBm, PAE ${}_{\text {1dB}} \geq 22$ % in 21.5-36.1 GHz (50.7% FBW).