Towards Segmentation-Based Address Translation for LLM Inference

IF 2 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2026-03-15 DOI:10.1109/LCA.2026.3693796
Youngjoon Cheon;Yunho Oh;Jeongseob Ahn
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引用次数: 0

Abstract

As large language models (LLMs) continue to scale in both model size and context length, the efficiency of address translation has become a critical performance bottleneck during inference. Although LLM inference accesses model weights in a layer-wise pattern with substantial reuse across token generations, the expanding KV-cache footprint increasingly contends for TLB capacity, leaving fewer entries to cache weight translations. In this letter, we revisit segmentation-based address translation for model weights to bypass conventional TLB-based translation. Since model weights are read-only and not reclaimed for the lifetime of a serving instance, the segmentation-based address translation is well-suited to this access pattern. We place model weights in a virtually contiguous region backed by a physically contiguous memory, enabling segment-based translation that minimizes address translation overhead. Our evaluation shows that the proposed design improves overall IPC by 2.51 × over the paging baseline by achieving near-zero translation overhead for model weights.
基于分段的LLM推理地址转换研究
随着大型语言模型(llm)在模型大小和上下文长度上的不断扩展,地址翻译的效率已经成为推理过程中一个关键的性能瓶颈。尽管LLM推理以分层模式访问模型权重,并在令牌代之间进行大量重用,但不断扩展的kv -缓存占用越来越多地争夺TLB容量,从而留下更少的条目来缓存权重转换。在这封信中,我们重新讨论了模型权重的基于分段的地址翻译,以绕过传统的基于tlb的翻译。由于模型权重是只读的,并且在服务实例的生命周期内不会被回收,因此基于分段的地址转换非常适合这种访问模式。我们将模型权重放在一个由物理上连续的内存支持的几乎连续的区域中,从而实现基于段的转换,从而最大限度地减少地址转换开销。我们的评估表明,通过实现模型权重的转换开销接近于零,所提出的设计在分页基线上将总体IPC提高了2.51倍。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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