Rules, Not Rankings: Interpretable AI for Processor Microarchitecture Design Analysis

IF 2 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2026-03-13 DOI:10.1109/LCA.2026.3692901

Abdoulaye Gamatié;Lincen Yang;Paulo Pimenta

引用次数: 0

Abstract

Expert-driven microarchitecture analysis provides valuable insights but fails to scale to modern design spaces, while black-box AI offers scalability at the cost of interpretability. We present PTAH, a data-driven methodology that combines codified expert knowledge with an interpretable conditional-density model. PTAH derives human-readable rules that link processor mechanism configurations to the full IPC probability distribution. Clustering these rules yields design principles that highlight key interactions, trade-offs, and behavioral regimes. A case study on SPEC CPU workloads shows that PTAH uncovers design insights while preserving full interpretability.

查看原文本刊更多论文

规则，而不是排名：处理器微架构设计分析的可解释AI

专家驱动的微架构分析提供了有价值的见解，但无法扩展到现代设计空间，而黑盒人工智能以可解释性为代价提供可扩展性。我们提出了PTAH，这是一种数据驱动的方法，将编纂的专家知识与可解释的条件密度模型相结合。PTAH派生出人类可读的规则，这些规则将处理器机制配置链接到完整的IPC概率分布。将这些规则聚集在一起，就产生了突出关键交互、权衡和行为机制的设计原则。一个关于SPEC CPU工作负载的案例研究表明，PTAH在保留完全可解释性的同时揭示了设计见解。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.