MMC: Metadata Migration for Efficient Memory Management in CXL DRAM Systems

IF 2 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2026-04-24 DOI:10.1109/LCA.2026.3687345
Dusol Lee;Taehyung Lee;Hanseon Lee;Nam Sung Kim;Jihong Kim
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引用次数: 0

Abstract

CXL-DRAM enables cost-efficient memory expansion in data-center servers, but introduces new challenges for operating system memory management. In particular, large in-kernel metadata structures can occupy a significant portion of DDR-DRAM, reducing the space available for application data and increasing accesses to slower CXL-DRAM. Placing all metadata in CXL-DRAM frees DDR-DRAM space but can cause severe tail latency due to inefficient memory reclamation. We propose MMC, a hot–cold metadata migration mechanism that balances application performance and reclamation efficiency by dynamically placing metadata across DDR-DRAM and CXL-DRAM. Our results show that MMC improves throughput while reducing tail latency across diverse workloads.
CXL DRAM系统中高效内存管理的元数据迁移
CXL-DRAM可以在数据中心服务器中实现经济高效的内存扩展,但也为操作系统内存管理带来了新的挑战。特别是,大型内核内元数据结构可能占用DDR-DRAM的很大一部分,从而减少了应用程序数据的可用空间,增加了对较慢的CXL-DRAM的访问。将所有元数据放在xml - dram中可以释放DDR-DRAM空间,但由于内存回收效率低下,可能会导致严重的尾部延迟。我们提出了MMC,一种冷热元数据迁移机制,通过动态地将元数据放置在DDR-DRAM和CXL-DRAM之间来平衡应用程序性能和回收效率。我们的结果表明,MMC提高了吞吐量,同时减少了不同工作负载之间的尾部延迟。
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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