Junzhe Jing;Feng Min;Yiming Gan;Ying Wang;Yinhe Han
{"title":"CGR-NPU: A Hybrid CGRA and NPU Architecture for Adaptive Neural Computing Workloads","authors":"Junzhe Jing;Feng Min;Yiming Gan;Ying Wang;Yinhe Han","doi":"10.1109/LCA.2025.3647885","DOIUrl":null,"url":null,"abstract":"To exploit apabilities of processors in contemporary heterogeneous systems, frequent data movement across disparate memory domains is required. The substantial overhead incurred by this data transfer is now a principal bottleneck for system performance, especially for computationally intensive, large-scale AI workloads. To address this, we propose CGR-NPU, a hybrid architecture that synergistically combines a Coarse-Grained Reconfigurable Array (CGRA) with a Neural Processing Unit (NPU). The architecture features tightly-coupled CGRA and NPU operational modes with fast switching, and leverages a reinforcement learning-based mechanism for dynamic resource allocation tailored to workload characteristics. Evaluations on diverse ML benchmarks show our integrated architecture improves average 1.62× performance speed up and reduces silicon area by 48.4% compared to standalone CGRA or NPU baselines. The overhead for mode switching and internal data handling is minimal, constituting only 7% of the total execution time.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 1","pages":"81-84"},"PeriodicalIF":2.0000,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Computer Architecture Letters","FirstCategoryId":"94","ListUrlMain":"https://ieeexplore.ieee.org/document/11314655/","RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"2025/12/24 0:00:00","PubModel":"Epub","JCR":"Q4","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
To exploit apabilities of processors in contemporary heterogeneous systems, frequent data movement across disparate memory domains is required. The substantial overhead incurred by this data transfer is now a principal bottleneck for system performance, especially for computationally intensive, large-scale AI workloads. To address this, we propose CGR-NPU, a hybrid architecture that synergistically combines a Coarse-Grained Reconfigurable Array (CGRA) with a Neural Processing Unit (NPU). The architecture features tightly-coupled CGRA and NPU operational modes with fast switching, and leverages a reinforcement learning-based mechanism for dynamic resource allocation tailored to workload characteristics. Evaluations on diverse ML benchmarks show our integrated architecture improves average 1.62× performance speed up and reduces silicon area by 48.4% compared to standalone CGRA or NPU baselines. The overhead for mode switching and internal data handling is minimal, constituting only 7% of the total execution time.
期刊介绍:
IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.