CGR-NPU: A Hybrid CGRA and NPU Architecture for Adaptive Neural Computing Workloads

IF 2 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2025-12-24 DOI:10.1109/LCA.2025.3647885
Junzhe Jing;Feng Min;Yiming Gan;Ying Wang;Yinhe Han
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引用次数: 0

Abstract

To exploit apabilities of processors in contemporary heterogeneous systems, frequent data movement across disparate memory domains is required. The substantial overhead incurred by this data transfer is now a principal bottleneck for system performance, especially for computationally intensive, large-scale AI workloads. To address this, we propose CGR-NPU, a hybrid architecture that synergistically combines a Coarse-Grained Reconfigurable Array (CGRA) with a Neural Processing Unit (NPU). The architecture features tightly-coupled CGRA and NPU operational modes with fast switching, and leverages a reinforcement learning-based mechanism for dynamic resource allocation tailored to workload characteristics. Evaluations on diverse ML benchmarks show our integrated architecture improves average 1.62× performance speed up and reduces silicon area by 48.4% compared to standalone CGRA or NPU baselines. The overhead for mode switching and internal data handling is minimal, constituting only 7% of the total execution time.
CGR-NPU:一种用于自适应神经计算工作负载的CGRA和NPU混合架构
为了在当代异构系统中利用处理器的能力,需要在不同的内存域之间频繁地移动数据。这种数据传输产生的大量开销现在是系统性能的主要瓶颈,特别是对于计算密集型、大规模的人工智能工作负载。为了解决这个问题,我们提出了CGR-NPU,这是一种将粗粒度可重构阵列(CGRA)与神经处理单元(NPU)协同结合的混合架构。该架构具有紧密耦合的CGRA和NPU运行模式,具有快速切换功能,并利用基于强化学习的机制,根据工作负载特征进行动态资源分配。对各种ML基准测试的评估表明,与独立的CGRA或NPU基准相比,我们的集成架构平均提高了1.62倍的性能速度,并减少了48.4%的硅面积。模式切换和内部数据处理的开销很小,仅占总执行时间的7%。
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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