WITHDRAWAL: Memristor based 8 T SRAM Cell with New Reliability Concern on noise voltage parameter for Neuromorphic Memory for Smart Industries

IF 1.8 4区 工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC
Iet Circuits Devices & Systems Pub Date : 2025-12-12 Epub Date: 2026-07-19 DOI:10.1049/cds2.12146
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引用次数: 0

Abstract

WITHDRAWAL: Z. Gupta, P. K. Rai, T. Pandey, M. Shabaz, V. Mishra, S. Akashe, P. Pundhir, “Memristor based 8 T SRAM Cell with New Reliability Concern on noise voltage parameter for Neuromorphic Memory for Smart Industries”, IET Circuits, Devices & Systems (2025): e12146. https://ietresearch.onlinelibrary.wiley.com/doi/10.1049/cds2.12146

The above article, published online on 12 December 2025, on Wiley Online Library (wileyonlinelibrary.com), has been withdrawn by agreement between the Institution of Engineering and Technology and John Wiley & Sons Ltd. UK. The withdrawal has been agreed as this manuscript was under consideration but the journal decided not to proceed with publication and informed the authors about this. Despite this decision, the article was subsequently published due to a technical error on the part of Wiley, the publisher, as an unedited accepted article prior to the version of record.

基于记忆电阻器的8 T SRAM单元及其对智能工业神经形态存储器噪声电压参数可靠性的新关注
引用本文:古普塔,潘迪,夏巴兹,s.a Akashe, P. Pundhir,“基于噪声电压参数的8 T SRAM单元可靠性研究”,电子工程学报,2025,第6卷第1期。https://ietresearch.onlinelibrary.wiley.com/doi/10.1049/cds2.12146The以上文章于2025年12月12日在Wiley在线图书馆(wileyonlinelibrary.com)上发表,经工程技术学会和约翰·威利父子有限公司协议撤回。英国。由于该手稿正在考虑中,因此已同意撤回,但期刊决定不继续发表并通知了作者。尽管做出了这样的决定,但由于出版商Wiley的一个技术错误,这篇文章随后被发表为未编辑的接受文章,而不是记录版本。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
Iet Circuits Devices & Systems
Iet Circuits Devices & Systems 工程技术-工程:电子与电气
CiteScore
3.80
自引率
7.70%
发文量
32
审稿时长
3 months
期刊介绍: IET Circuits, Devices & Systems covers the following topics: Circuit theory and design, circuit analysis and simulation, computer aided design Filters (analogue and switched capacitor) Circuit implementations, cells and architectures for integration including VLSI Testability, fault tolerant design, minimisation of circuits and CAD for VLSI Novel or improved electronic devices for both traditional and emerging technologies including nanoelectronics and MEMs Device and process characterisation, device parameter extraction schemes Mathematics of circuits and systems theory Test and measurement techniques involving electronic circuits, circuits for industrial applications, sensors and transducers
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