Unveiling the impact of ITCs on High-k SOI GaN FinFET and its sensitivity analysis for improved reliability: a simulation study

Abstract

This study examined the effects of different interface trap charges on High-k SOI GaN FinFET at short channel length, and the outcomes were contrasted with those of Si FinFET. The analog performance is compared through parameters such as subthreshold swing (SS), current ratio (I_ON/I_OFF) and threshold voltage (V_Th). Acceptor traps affect both devices more than donor traps do, due to their tendency to become positively charged and unscreened under typical operating conditions. High-k SOI GaN FinFETs have lower V_Th and SS shifts (5% & 1.3%, respectively) than Si FinFETs (11% & 23%, respectively) due to a combination of factors, including a higher bandgap and larger oxide capacitance. Also, the effect of temperature on the DC parameters of the proposed device under various trap charges has been investigated. Furthermore, sensitivity analysis for the proposed device under donor and acceptor trap charges, varying temperature, metal work function, and various doping concentrations across the source, drain, and channel regions, has been performed. Results reveal that the proposed device is more sensitive to acceptor traps than to donor traps. Under acceptor traps, the proposed device provides sensitivities of 100, 98, 108, and 101 for metal work function, source doping, drain doping, and channel doping variation, respectively.