MFrodo: Efficient and Memory-Sensitive Simulink Code Generation via Redundancy Elimination

Abstract

Simulink has emerged as the fundamental infrastructure that supports modeling, simulation, verification, and code generation for embedded software development. To improve the performance of the code generated from Simulink models, state-of-the-art code generators employ various optimization techniques, such as expression folding, variable reuse, and parallelism. However, they overlook the presence of redundant calculations within data-intensive models widely used to perform substantial data processing in embedded scenarios, which can significantly degrade the performance and introduce additional memory usage. This article proposes MFrodo, an efficient and memory-sensitive code generator for data-intensive Simulink models through redundancy elimination. MFrodo begins by conducting model analysis to construct the dataflow graph and derive the input/output (I/O) mapping of each block. Then, for each block within the dataflow graph, MFrodo recursively determines its calculation range by leveraging the I/O mapping of its subsequent blocks and marks optimization blocks whose calculation range is eliminated. For optimizable blocks, MFrodo eliminates the redundant calculations and reduces the memory space associated with these calculations. Finally, MFrodo rebuilds the I/O mappings of these optimizable blocks to ensure code correctness and synthesizes the embedded code for deployment. We implemented and evaluated MFrodo on benchmark Simulink models, in terms of execution duration, memory usage, and code generation overhead across different compilers and architectures. The results show that, compared with the Simulink Embedded Coder, DFSynth, and HCG, MFrodo achieves performance improvements ranging from $1.17\times $ to $8.55\times $ , while reducing BSS segment usage by 12.00%–52.71%. Besides, MFrodo reduces compile time by 91.8%–98.7% and code synthesis time by 94.3%–99.6% compared with Simulink Embedded Coder, while incurring comparable overhead to DFSynth and HCG.