{"title":"A Markov-Chain-Based PUF Using Chain-Block-Obfuscation Mechanism Resisting Machine Learning Attacks With High Uniformity Robustness","authors":"Junhong Gan;Hanqing Luo;Yuanfeng Xie;Liping Liang","doi":"10.1109/TCAD.2025.3634218","DOIUrl":null,"url":null,"abstract":"Physical unclonable functions (PUFs) are lightweight hardware security primitives suitable for resource-constrained Internet of Things (IoT) devices. The arbiter PUF (APUF), as a classic strong PUF structure, is well-suited for lightweight device authentication. Unfortunately, due to certain structural characteristics, the classic APUF can be successfully modeled by various machine learning (ML) models with only a small number of challenge-response pair (CRP) samples. To address this security issue, in this article, we build upon the classic APUF structure by introducing a chain block obfuscation (CBO) mechanism and a Markov obfuscation mechanism at the input and output stages, respectively. This approach demonstrates strong resistance against four ML models—logistic regression (LR), support vector machine (SVM), covariance matrix adaptation evolutionary strategies (CMA-ES), and artificial neural networks (ANNs)—while optimizing hardware resource usage by at least 53.4% compared to previous attack-resistant structures. Even with up to 2M CRPs for training, the prediction accuracy remains around 50%. Additionally, <sc>xor</small>, a widely adopted output obfuscation mechanism by many researchers, has limitations in output uniformity when the number of intrachip parallel APUFs is small. Studies have shown that the uniqueness between intrachip APUFs may not reach the ideal value of 50%. In such cases, especially when there are only two parallel APUFs in the circuit, the uniformity of the <sc>xor</small> output is affected by insufficient uniqueness. To address this issue, this article proposes a MUX-based Markov output obfuscation mechanism. Experimental data on the Xilinx Artix-7 field-programmable gate array (FPGA) platform demonstrate that this mechanism exhibits strong robustness in uniformity compared to the traditional <sc>xor</small> output obfuscation, particularly when the number of intrachip parallel APUFs is small.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3526-3539"},"PeriodicalIF":3.6000,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","FirstCategoryId":"94","ListUrlMain":"https://ieeexplore.ieee.org/document/11251279/","RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"2025/11/18 0:00:00","PubModel":"Epub","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
Physical unclonable functions (PUFs) are lightweight hardware security primitives suitable for resource-constrained Internet of Things (IoT) devices. The arbiter PUF (APUF), as a classic strong PUF structure, is well-suited for lightweight device authentication. Unfortunately, due to certain structural characteristics, the classic APUF can be successfully modeled by various machine learning (ML) models with only a small number of challenge-response pair (CRP) samples. To address this security issue, in this article, we build upon the classic APUF structure by introducing a chain block obfuscation (CBO) mechanism and a Markov obfuscation mechanism at the input and output stages, respectively. This approach demonstrates strong resistance against four ML models—logistic regression (LR), support vector machine (SVM), covariance matrix adaptation evolutionary strategies (CMA-ES), and artificial neural networks (ANNs)—while optimizing hardware resource usage by at least 53.4% compared to previous attack-resistant structures. Even with up to 2M CRPs for training, the prediction accuracy remains around 50%. Additionally, xor, a widely adopted output obfuscation mechanism by many researchers, has limitations in output uniformity when the number of intrachip parallel APUFs is small. Studies have shown that the uniqueness between intrachip APUFs may not reach the ideal value of 50%. In such cases, especially when there are only two parallel APUFs in the circuit, the uniformity of the xor output is affected by insufficient uniqueness. To address this issue, this article proposes a MUX-based Markov output obfuscation mechanism. Experimental data on the Xilinx Artix-7 field-programmable gate array (FPGA) platform demonstrate that this mechanism exhibits strong robustness in uniformity compared to the traditional xor output obfuscation, particularly when the number of intrachip parallel APUFs is small.
期刊介绍:
The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components. The aids include methods, models, algorithms, and man-machine interfaces for system-level, physical and logical design including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, hardware-software co-design and documentation of integrated circuit and system designs of all complexities. Design tools and techniques for evaluating and designing integrated circuits and systems for metrics such as performance, power, reliability, testability, and security are a focus.