Hardware-Accelerated Parallel Wrong-Path Execution for Spectre Gadget Detection

IF 2 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2026-06-04 DOI:10.1109/LCA.2026.3700174

Fangzheng Lin;Zeyu Gao;Yanru Lin;Yangyu Chen;Hiroshi Sasaki

引用次数: 0

Abstract

Spectre vulnerabilities pose new threats to computer system security, and detecting Spectre gadgets is an important step toward effective countermeasures. Detection requires exploring program behavior along branch-mispredicted execution paths (i.e., wrong paths), which existing dynamic scanners emulate in software—incurring high overhead and limiting parallel exploration. This paper proposes a hardware-assisted dynamic gadget detection architecture that offloads wrong-path executions to a pool of in-order shadow cores on a specialized asymmetric multicore platform, enabling multiple paths to be explored in parallel. The design also features shadow memory versioning to preserve the memory view at the branch point without full memory duplication. We prototype the proposed architecture on an Xilinx VU13P FPGA. Evaluation shows that the prototype achieves 1.25–5.24 × speedup over software-based detectors.

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用于幽灵小工具检测的硬件加速并行错误路径执行

Spectre漏洞对计算机系统安全构成了新的威胁，检测Spectre小工具是有效应对的重要一步。检测需要沿着分支——错误预测的执行路径（即错误的路径）探索程序行为，现有的动态扫描器在软件中模拟这些行为——导致高开销并限制并行探索。本文提出了一种硬件辅助的动态小部件检测体系结构，该体系结构将错误路径的执行卸载到专用的非对称多核平台上的有序影子核池中，使多条路径能够并行探索。该设计还具有影子内存版本控制功能，以保留分支点的内存视图，而不需要完全内存复制。我们在Xilinx VU13P FPGA上对所提出的架构进行了原型设计。评估表明，该原型比基于软件的检测器实现了1.25-5.24倍的加速。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.