Privilege Level Dynamics and Their Impact on Conditional Branch Prediction Performance in FaaS

IF 2 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2026-07-01 Epub Date: 2026-06-12 DOI:10.1109/LCA.2026.3703184

Louka Yerly;Arthur Perais

引用次数: 0

Abstract

Cloud providers are proposing microservice-based infrastructures in the form of Function-as-a-Service (FaaS) offerings. These workloads are very short-lived and spend significant time in privileged execution as they communicate collectively through the network. Current processors are not well adapted to running these workloads as the many predictors and caches used to provide performance struggle to warmup due to the short duration of Functions. This work thoroughly analyzes the interplay of user and privileged execution in a set of FaaS workloads and its impact on conditional branch prediction, which is a critical performance and efficiency feature. We first highlight that execution mode changes at high frequency, and that few (around 10

$^{3}$

) instructions are executed in a given mode before switching. We then provide possible directions to improve CBP performance on such workloads.

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权限级别动态及其对FaaS中条件分支预测性能的影响

云提供商正在以功能即服务（FaaS）产品的形式提出基于微服务的基础设施。这些工作负载非常短暂，并且在特权执行中花费大量时间，因为它们通过网络进行集体通信。当前的处理器不能很好地适应运行这些工作负载，因为用于提供性能的许多预测器和缓存由于函数持续时间短而难以预热。这项工作彻底分析了一组FaaS工作负载中用户和特权执行的相互作用及其对条件分支预测的影响，这是一个关键的性能和效率特征。我们首先强调，执行模式的变化频率很高，并且在切换之前，在给定模式下执行的指令很少（大约10$^{3}$）。然后，我们提供了在这种工作负载上改进CBP性能的可能方向。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.