A 1280 × 1024 SWIR DROIC With Self-Correcting Phase-Coded TDC-Interpolated Single-Slope ADC

Abstract

This brief presents a $1280\times 1024$ pixel-array, $10~\boldsymbol {\mu }$ m-pitch digital readout integrated circuit (DROIC), fabricated in a 180-nm CMOS process and hybrid-integrated with an InGaAs sensor array for megapixel-level short-wave infrared (SWIR) imaging. The DROIC employs a column-parallel analog-to-digital converter (ADC) architecture, in which a 2-bit time-to-digital converter (TDC) is incorporated into a 12-bit single-slope (SS) ADC to quantize the residual signal. A chip-shared multiphase clock generator scheme is adopted to provide uniform phase references with small area and low power overhead. To address coarse-fine stitching errors caused by chip-shared multiphase clock distribution, a self-correcting phase-coded stitching scheme is proposed. The proposed self-correcting phase-coded stitching scheme mitigates SNR degradation and improves column-to-column uniformity by suppressing jump code errors. The hybrid-integrated SWIR focal-plane array (FPA) achieves an array-averaged SNR of 83.44 dB and a random noise of $4.2~\boldsymbol {\mathrm {e^{-}_{rms}}}$ , while the measured dark fixed-pattern noise (FPN) is 0.11%. The FPA consumes 408 mW at a frame rate of 60 Hz, achieving a power efficiency of 427.16 fJ/LSB. These results demonstrate excellent noise performance, low FPN, and high energy efficiency for megapixel-level SWIR imaging.