ANP-R: A 22nm 0.88pJ/SOP Asynchronous SNN-based Processor with Coarse-Grained Reconfigurable Architecture Enabling Multisensory On-chip Incremental Learning for Edge AI.

Abstract

Spiking Neural Networks (SNNs) have emerged as a promising paradigm for brain-inspired edge computing. Leveraging binary spikes and local learning rules, SNNs enable energy-efficient on-chip learning and rapid adaptation to changing environments, which is crucial for edge AI that needs to learn continuously from new data. However, many SNN processors enabling on-chip learning for edge computing confront a trade-off: small-scale task-specific designs offer low power but poor multi-task inference accuracy, while large-scale general-purpose designs achieve high multi-task accuracy at the cost of large memory and poor energy efficiency. To overcome this challenge, this paper presents ANP-R, a 22nm asynchronous SNN-based edge AI processor with coarse-grained reconfigurable architecture enabling one-shot, few-shot, batch and incremental on-chip learning. The processor integrates 64 cores containing 4096 neurons and 0.262 million synapses. Two key features are proposed: 1) An asynchronous coarse-grained reconfigurable architecture that supports various STDP-based SNN topologies. These topologies enable over 95% average accuracy across four sensory tasks; 2) an energy-efficient asynchronous training method incorporating a self-adaptive synaptic weight update mechanism reducing up to 65% redundant updates without accuracy loss, and a trained weights low-bit width coding method reducing up to 50% storage cost with 0.3% accuracy loss. Measurement results demonstrate 92.1% accuracy for hand gesture classification, 93.9% for keyword spotting, 98.6% for object recognition and 99.2% for gas identification. Compared with state-of-the-art SNN-based chips, this work achieves up to 6.02x, 8.61x and 7.1% improvement in energy efficiency, energy per step, and accuracy, respectively.