PIAT: Unleashing Memory Parallelism via Power-Interference-Aware Timing Control

Abstract

Modern DRAM leverages bank-level parallelism to hide long access latency and sustain high throughput. However, shared on-die power resources restrict concurrent bank operations through timing parameters, which are set to uniform worst-case bounds even though power interference varies with the spatial relationship and concurrency of activations. This pessimism wastes parallelism and limits aggressive schemes such as Subarray-Level Parallelism (SALP). We propose Power-Interference-Aware Timing (PIAT), a timing control mechanism that adapts DRAM AC timing to expected power interference. PIAT selectively relaxes timing constraints based on physical separation and activation concurrency while preserving conservative timing for high-interference cases. This controller-side approach improves memory parallelism without DRAM hardware changes, achieving 0.8%–8.1% gains in the 32-bank configuration and 3.5%–88.9% in the 64-bank configuration across various SALP settings.