Differential Privacy for Secure Cache Partitioning: Promises, Limits, and Fixes

IF 2 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
IEEE Computer Architecture Letters Pub Date : 2026-01-01 Epub Date: 2026-03-27 DOI:10.1109/LCA.2026.3697544
Prerna Priyadarshini;Abhijat Bharadwaj;Biswabandan Panda
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引用次数: 0

Abstract

The shared last-level cache (LLC) enables cross-core contention-based attacks. While LLC randomization mitigates conflict-based attacks, cache partitioning prevents all attack classes. Recent secure partitioning techniques dynamically allocate LLC space and claim security against cache occupancy attacks. We show that state-of-the-art LLC usage-based dynamic partitioning remains vulnerable. Focusing on Secure and Scalable Cache Partitioning (SCALE), which applies differential privacy–based noise to LLC way allocations, we demonstrate that allocations can be denoised over time to construct a reliable LLC occupancy channel. The key insight that drives the occupancy channel is that differential privacy protects individual allocations; it does not hide long-term statistics such as the mean, median, and standard deviation. We showcase a novel LLC occupancy attack that does application fingerprint exploiting statistical properties. Finally, we propose lightweight fixes that mitigate this leakage.
安全缓存分区的差异隐私:承诺、限制和修复
共享的最后一级缓存(LLC)支持基于争用的跨核攻击。虽然有限责任随机化减轻了基于冲突的攻击,但缓存分区可以防止所有攻击类。最近的安全分区技术动态分配LLC空间,并声称安全对抗缓存占用攻击。我们展示了最先进的基于LLC使用的动态分区仍然是脆弱的。关注安全可扩展缓存分区(SCALE),它将基于隐私的差异噪声应用于LLC方式分配,我们证明了分配可以随着时间的推移去噪,以构建可靠的LLC占用通道。驱动占用通道的关键洞见是,差异隐私保护个人分配;它不会隐藏长期统计数据,如平均值、中位数和标准差。我们展示了一种新颖的LLC占用攻击,它利用统计属性进行应用指纹识别。最后,我们提出了减轻这种泄漏的轻量级修复。
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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